[llvm] r347274 - Implement computeKnownBits for scalar_to_vector
Stanislav Mekhanoshin via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 19 15:34:07 PST 2018
Author: rampitec
Date: Mon Nov 19 15:34:07 2018
New Revision: 347274
URL: http://llvm.org/viewvc/llvm-project?rev=347274&view=rev
Log:
Implement computeKnownBits for scalar_to_vector
Differential Revision: https://reviews.llvm.org/D54728
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=347274&r1=347273&r2=347274&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Nov 19 15:34:07 2018
@@ -2345,6 +2345,19 @@ KnownBits SelectionDAG::computeKnownBits
}
break;
}
+ case ISD::SCALAR_TO_VECTOR: {
+ // We know about scalar_to_vector as much as we know about it source,
+ // which becomes the first element of otherwise unknown vector.
+ if (DemandedElts != 1)
+ break;
+
+ SDValue N0 = Op.getOperand(0);
+ Known = computeKnownBits(N0, DemandedElts, Depth + 1);
+ if (N0.getValueSizeInBits() != BitWidth)
+ Known = Known.trunc(BitWidth);
+
+ break;
+ }
case ISD::BITCAST: {
SDValue N0 = Op.getOperand(0);
EVT SubVT = N0.getValueType();
Modified: llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll?rev=347274&r1=347273&r2=347274&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/load-lo16.ll Mon Nov 19 15:34:07 2018
@@ -305,8 +305,11 @@ entry:
; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64
-; VI: flat_load_ubyte v{{[0-9]+}}
-; VI: v_or_b32_e32
+; VI: flat_load_ubyte [[LO:v[0-9]+]]
+; VI: v_lshrrev_b32_e32 [[HI:v[0-9]+]], 16, v2
+; VI: s_mov_b32 [[MASK:s[0-9]+]], 0x5040c00
+; VI: v_perm_b32 [[RES:v[0-9]+]], [[HI]], [[LO]], [[MASK]]
+; VI: flat_store_dword v[0:1], [[RES]]
define void @load_flat_lo_v2i16_reglo_vreg_zexti8(i8* %in, i32 %reg) #0 {
entry:
%reg.bc = bitcast i32 %reg to <2 x i16>
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