[PATCH] D54648: [TableGen] Emit more variant transitions

[Evandro Menezes via Phabricator via llvm-commits]

evandro updated this revision to Diff 174684.
evandro edited the summary of this revision.
evandro added a comment.
Herald added subscribers: gbedwell, javed.absar.

Exclude test that does not apply anymore.


https://reviews.llvm.org/D54648

Files:
  llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s
  llvm/utils/TableGen/SubtargetEmitter.cpp


Index: llvm/utils/TableGen/SubtargetEmitter.cpp
===================================================================
--- llvm/utils/TableGen/SubtargetEmitter.cpp
+++ llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -1504,9 +1504,9 @@
       continue;
 
     if (OnlyExpandMCInstPredicates) {
-      // Ignore this variant scheduling class if transitions don't uses any
+      // Ignore this variant scheduling class if no transitions use any
       // MCSchedPredicate definitions.
-      if (!all_of(SC.Transitions, [](const CodeGenSchedTransition &T) {
+      if (!any_of(SC.Transitions, [](const CodeGenSchedTransition &T) {
             return hasMCSchedPredicates(T);
           }))
         continue;
@@ -1560,6 +1560,7 @@
     PE.setExpandForMC(OnlyExpandMCInstPredicates);
     for (unsigned PI : ProcIndices) {
       OS << "    ";
+
       // Emit a guard on the processor ID.
       if (PI != 0) {
         OS << (OnlyExpandMCInstPredicates
@@ -1573,11 +1574,20 @@
       for (const CodeGenSchedTransition &T : SC.Transitions) {
         if (PI != 0 && !count(T.ProcIndices, PI))
           continue;
+
+        // Emit only transitions based on MCSchedPredicate, if it's the case.
+        // At least the transition specified by NoSchedPred is emitted,
+        // which becomes the default transition for those variants otherwise
+        // not based on MCSchedPredicate .
+        if (OnlyExpandMCInstPredicates && !hasMCSchedPredicates(T))
+          continue;
+
         PE.setIndentLevel(3);
         emitPredicates(T, SchedModels.getSchedClass(T.ToClassIdx), PE, OS);
       }
 
       OS << "    }\n";
+
       if (PI == 0)
         break;
     }
Index: llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s
===================================================================
--- llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s
+++ llvm/test/tools/llvm-mca/ARM/unsupported-write-variant.s
@@ -1,4 +1,5 @@
 # RUN: not llvm-mca -march=arm -mcpu=swift -all-views=false 2>&1 < %s | FileCheck %s
+# XFAIL: *
 
 add r3, r1, r12, lsl #2
 


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