[llvm] r347218 - [Hexagon] make test immune to improvements in undef simplification

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Mon Nov 19 07:34:09 2018
New Revision: 347218

URL: http://llvm.org/viewvc/llvm-project?rev=347218&view=rev
Log:
[Hexagon] make test immune to improvements in undef simplification

Modified:
    llvm/trunk/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll

Modified: llvm/trunk/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll?rev=347218&r1=347217&r2=347218&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/build-vector-i32-type.ll Mon Nov 19 07:34:09 2018
@@ -9,11 +9,11 @@ target triple = "hexagon"
 @g0 = global <16 x float> zeroinitializer, align 8
 @g1 = global <16 x i32> zeroinitializer, align 8
 
-define void @fred() #0 {
+define void @fred(<16 x i16> %x) #0 {
 b0:
   %v1 = load <16 x float>, <16 x float>* @g0, align 8
   %v2 = fcmp olt <16 x float> undef, %v1
-  %v3 = select <16 x i1> %v2, <16 x i16> undef, <16 x i16> zeroinitializer
+  %v3 = select <16 x i1> %v2, <16 x i16> %x, <16 x i16> zeroinitializer
   %v4 = sext <16 x i16> %v3 to <16 x i32>
   store <16 x i32> %v4, <16 x i32>* @g1, align 64
   ret void