[PATCH] D54700: [PowerPC] Add Itineraries for STWU/STWUX etc

[Jinsong Ji via Phabricator via llvm-commits]

jsji created this revision.
jsji added reviewers: nemanjai, hfinkel, stefanp, steven.zhang.
Herald added subscribers: kbarton, hiraditya.

When doing some instruction scheduling work, we noticed some missing itineraries.

Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, 
because we can still get same latency due to default values.

With machine scheduler, however, itineraries will have impact to scheduling.
eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class.
And most of the instruction class with itineraries will have NumMicroOps default to 1.

This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, 
then causing different scheduling or suboptimal scheduling further.

This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for https://reviews.llvm.org/P8.

Since there are already multiple IIC for store update, this patch also merge
IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU
IIC_LdStSTDUX to IIC_LdStSTUX

and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference.


https://reviews.llvm.org/D54700

Files:
  llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCSchedule.td
  llvm/lib/Target/PowerPC/PPCSchedule440.td
  llvm/lib/Target/PowerPC/PPCScheduleA2.td
  llvm/lib/Target/PowerPC/PPCScheduleE500.td
  llvm/lib/Target/PowerPC/PPCScheduleE500mc.td
  llvm/lib/Target/PowerPC/PPCScheduleE5500.td
  llvm/lib/Target/PowerPC/PPCScheduleG3.td
  llvm/lib/Target/PowerPC/PPCScheduleG4.td
  llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td
  llvm/lib/Target/PowerPC/PPCScheduleG5.td
  llvm/lib/Target/PowerPC/PPCScheduleP7.td
  llvm/lib/Target/PowerPC/PPCScheduleP8.td
  llvm/test/CodeGen/PowerPC/stwu-sched.ll

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