[llvm] r347177 - [X86][SSE] Add SimplifyDemandedVectorElts support for SSE packed i2fp conversions.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 18 14:13:31 PST 2018
Author: rksimon
Date: Sun Nov 18 14:13:31 2018
New Revision: 347177
URL: http://llvm.org/viewvc/llvm-project?rev=347177&view=rev
Log:
[X86][SSE] Add SimplifyDemandedVectorElts support for SSE packed i2fp conversions.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/pr30511.ll
llvm/trunk/test/CodeGen/X86/vec_int_to_fp-widen.ll
llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=347177&r1=347176&r2=347177&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Nov 18 14:13:31 2018
@@ -32193,6 +32193,17 @@ bool X86TargetLowering::SimplifyDemanded
return true;
break;
}
+ case X86ISD::CVTSI2P:
+ case X86ISD::CVTUI2P: {
+ SDValue Src = Op.getOperand(0);
+ EVT SrcVT = Src.getValueType();
+ APInt SrcUndef, SrcZero;
+ APInt SrcElts = DemandedElts.zextOrTrunc(SrcVT.getVectorNumElements());
+ if (SimplifyDemandedVectorElts(Src, SrcElts, SrcUndef, SrcZero, TLO,
+ Depth + 1))
+ return true;
+ break;
+ }
case X86ISD::VBROADCAST: {
SDValue Src = Op.getOperand(0);
MVT SrcVT = Src.getSimpleValueType();
@@ -38507,6 +38518,20 @@ static SDValue combineFMinNumFMaxNum(SDN
return DAG.getSelect(DL, VT, IsOp0Nan, Op1, MinOrMax);
}
+static SDValue combineX86INT_TO_FP(SDNode *N, SelectionDAG &DAG,
+ TargetLowering::DAGCombinerInfo &DCI) {
+ EVT VT = N->getValueType(0);
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+
+ APInt KnownUndef, KnownZero;
+ APInt DemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements());
+ if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef,
+ KnownZero, DCI))
+ return SDValue(N, 0);
+
+ return SDValue();
+}
+
/// Do target-specific dag combines on X86ISD::ANDNP nodes.
static SDValue combineAndnp(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
@@ -40887,6 +40912,8 @@ SDValue X86TargetLowering::PerformDAGCom
case X86ISD::FMAX: return combineFMinFMax(N, DAG);
case ISD::FMINNUM:
case ISD::FMAXNUM: return combineFMinNumFMaxNum(N, DAG, Subtarget);
+ case X86ISD::CVTSI2P:
+ case X86ISD::CVTUI2P: return combineX86INT_TO_FP(N, DAG, DCI);
case X86ISD::BT: return combineBT(N, DAG, DCI);
case ISD::ANY_EXTEND:
case ISD::ZERO_EXTEND: return combineZext(N, DAG, DCI, Subtarget);
Modified: llvm/trunk/test/CodeGen/X86/pr30511.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr30511.ll?rev=347177&r1=347176&r2=347177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr30511.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr30511.ll Sun Nov 18 14:13:31 2018
@@ -8,7 +8,6 @@ define i64 @PR30511(<2 x double> %a) {
; CHECK-LABEL: PR30511:
; CHECK: # %bb.0:
; CHECK-NEXT: addpd {{.*}}(%rip), %xmm0
-; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-NEXT: cvtdq2pd %xmm0, %xmm0
; CHECK-NEXT: mulpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: movq %xmm0, %rax
Modified: llvm/trunk/test/CodeGen/X86/vec_int_to_fp-widen.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_int_to_fp-widen.ll?rev=347177&r1=347176&r2=347177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_int_to_fp-widen.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_int_to_fp-widen.ll Sun Nov 18 14:13:31 2018
@@ -579,7 +579,7 @@ define <2 x double> @uitofp_2i64_to_2f64
define <2 x double> @uitofp_2i32_to_2f64(<4 x i32> %a) {
; SSE2-LABEL: uitofp_2i32_to_2f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0]
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,0,0,0,0]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE2-NEXT: psrld $16, %xmm0
@@ -591,7 +591,7 @@ define <2 x double> @uitofp_2i32_to_2f64
; SSE41-LABEL: uitofp_2i32_to_2f64:
; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE41-NEXT: psrld $16, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
@@ -602,7 +602,7 @@ define <2 x double> @uitofp_2i32_to_2f64
; VEX-LABEL: uitofp_2i32_to_2f64:
; VEX: # %bb.0:
; VEX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; VEX-NEXT: vcvtdq2pd %xmm1, %xmm1
; VEX-NEXT: vpsrld $16, %xmm0, %xmm0
; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0
@@ -643,7 +643,7 @@ define <2 x double> @uitofp_2i32_to_2f64
define <2 x double> @uitofp_4i32_to_2f64(<4 x i32> %a) {
; SSE2-LABEL: uitofp_4i32_to_2f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0]
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,0,0,0,0]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE2-NEXT: psrld $16, %xmm0
@@ -655,7 +655,7 @@ define <2 x double> @uitofp_4i32_to_2f64
; SSE41-LABEL: uitofp_4i32_to_2f64:
; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE41-NEXT: psrld $16, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
@@ -940,17 +940,18 @@ define <4 x double> @uitofp_4i32_to_4f64
; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE2-NEXT: movapd {{.*#+}} xmm2 = [6.5536E+4,6.5536E+4]
; SSE2-NEXT: mulpd %xmm2, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [65535,0,65535,0,0,0,0,0]
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
+; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: addpd %xmm1, %xmm0
-; SSE2-NEXT: movdqa %xmm3, %xmm1
+; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: psrld $16, %xmm1
-; SSE2-NEXT: cvtdq2pd %xmm1, %xmm4
-; SSE2-NEXT: mulpd %xmm2, %xmm4
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
-; SSE2-NEXT: cvtdq2pd %xmm3, %xmm1
-; SSE2-NEXT: addpd %xmm4, %xmm1
+; SSE2-NEXT: cvtdq2pd %xmm1, %xmm5
+; SSE2-NEXT: mulpd %xmm2, %xmm5
+; SSE2-NEXT: pand %xmm3, %xmm4
+; SSE2-NEXT: cvtdq2pd %xmm4, %xmm1
+; SSE2-NEXT: addpd %xmm5, %xmm1
; SSE2-NEXT: retq
;
; SSE41-LABEL: uitofp_4i32_to_4f64:
@@ -962,15 +963,16 @@ define <4 x double> @uitofp_4i32_to_4f64
; SSE41-NEXT: mulpd %xmm2, %xmm1
; SSE41-NEXT: pxor %xmm3, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4],xmm3[5],xmm0[6],xmm3[7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-NEXT: addpd %xmm1, %xmm0
-; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3,4,5,6,7]
-; SSE41-NEXT: psrld $16, %xmm4
-; SSE41-NEXT: cvtdq2pd %xmm4, %xmm4
-; SSE41-NEXT: mulpd %xmm2, %xmm4
-; SSE41-NEXT: cvtdq2pd %xmm3, %xmm1
-; SSE41-NEXT: addpd %xmm4, %xmm1
+; SSE41-NEXT: movdqa %xmm4, %xmm1
+; SSE41-NEXT: psrld $16, %xmm1
+; SSE41-NEXT: cvtdq2pd %xmm1, %xmm5
+; SSE41-NEXT: mulpd %xmm2, %xmm5
+; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0],xmm3[1],xmm4[2],xmm3[3],xmm4[4,5,6,7]
+; SSE41-NEXT: cvtdq2pd %xmm4, %xmm1
+; SSE41-NEXT: addpd %xmm5, %xmm1
; SSE41-NEXT: retq
;
; AVX1-LABEL: uitofp_4i32_to_4f64:
@@ -3510,7 +3512,7 @@ define <2 x double> @uitofp_load_2i32_to
; SSE41: # %bb.0:
; SSE41-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE41-NEXT: pxor %xmm1, %xmm1
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE41-NEXT: psrld $16, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
@@ -3522,7 +3524,7 @@ define <2 x double> @uitofp_load_2i32_to
; VEX: # %bb.0:
; VEX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; VEX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
+; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; VEX-NEXT: vcvtdq2pd %xmm1, %xmm1
; VEX-NEXT: vpsrld $16, %xmm0, %xmm0
; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0
@@ -3746,17 +3748,18 @@ define <4 x double> @uitofp_load_4i32_to
; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE2-NEXT: movapd {{.*#+}} xmm2 = [6.5536E+4,6.5536E+4]
; SSE2-NEXT: mulpd %xmm2, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [65535,0,65535,0,0,0,0,0]
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
+; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: addpd %xmm1, %xmm0
-; SSE2-NEXT: movdqa %xmm3, %xmm1
+; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: psrld $16, %xmm1
-; SSE2-NEXT: cvtdq2pd %xmm1, %xmm4
-; SSE2-NEXT: mulpd %xmm2, %xmm4
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
-; SSE2-NEXT: cvtdq2pd %xmm3, %xmm1
-; SSE2-NEXT: addpd %xmm4, %xmm1
+; SSE2-NEXT: cvtdq2pd %xmm1, %xmm5
+; SSE2-NEXT: mulpd %xmm2, %xmm5
+; SSE2-NEXT: pand %xmm3, %xmm4
+; SSE2-NEXT: cvtdq2pd %xmm4, %xmm1
+; SSE2-NEXT: addpd %xmm5, %xmm1
; SSE2-NEXT: retq
;
; SSE41-LABEL: uitofp_load_4i32_to_4f64:
@@ -3769,15 +3772,16 @@ define <4 x double> @uitofp_load_4i32_to
; SSE41-NEXT: mulpd %xmm2, %xmm1
; SSE41-NEXT: pxor %xmm3, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4],xmm3[5],xmm0[6],xmm3[7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-NEXT: addpd %xmm1, %xmm0
-; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3,4,5,6,7]
-; SSE41-NEXT: psrld $16, %xmm4
-; SSE41-NEXT: cvtdq2pd %xmm4, %xmm4
-; SSE41-NEXT: mulpd %xmm2, %xmm4
-; SSE41-NEXT: cvtdq2pd %xmm3, %xmm1
-; SSE41-NEXT: addpd %xmm4, %xmm1
+; SSE41-NEXT: movdqa %xmm4, %xmm1
+; SSE41-NEXT: psrld $16, %xmm1
+; SSE41-NEXT: cvtdq2pd %xmm1, %xmm5
+; SSE41-NEXT: mulpd %xmm2, %xmm5
+; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0],xmm3[1],xmm4[2],xmm3[3],xmm4[4,5,6,7]
+; SSE41-NEXT: cvtdq2pd %xmm4, %xmm1
+; SSE41-NEXT: addpd %xmm5, %xmm1
; SSE41-NEXT: retq
;
; AVX1-LABEL: uitofp_load_4i32_to_4f64:
Modified: llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll?rev=347177&r1=347176&r2=347177&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_int_to_fp.ll Sun Nov 18 14:13:31 2018
@@ -579,7 +579,7 @@ define <2 x double> @uitofp_2i64_to_2f64
define <2 x double> @uitofp_2i32_to_2f64(<4 x i32> %a) {
; SSE2-LABEL: uitofp_2i32_to_2f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0]
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,0,0,0,0]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE2-NEXT: psrld $16, %xmm0
@@ -591,7 +591,7 @@ define <2 x double> @uitofp_2i32_to_2f64
; SSE41-LABEL: uitofp_2i32_to_2f64:
; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE41-NEXT: psrld $16, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
@@ -602,7 +602,7 @@ define <2 x double> @uitofp_2i32_to_2f64
; VEX-LABEL: uitofp_2i32_to_2f64:
; VEX: # %bb.0:
; VEX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; VEX-NEXT: vcvtdq2pd %xmm1, %xmm1
; VEX-NEXT: vpsrld $16, %xmm0, %xmm0
; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0
@@ -643,7 +643,7 @@ define <2 x double> @uitofp_2i32_to_2f64
define <2 x double> @uitofp_4i32_to_2f64(<4 x i32> %a) {
; SSE2-LABEL: uitofp_4i32_to_2f64:
; SSE2: # %bb.0:
-; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0]
+; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,0,0,0,0]
; SSE2-NEXT: pand %xmm0, %xmm1
; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE2-NEXT: psrld $16, %xmm0
@@ -655,7 +655,7 @@ define <2 x double> @uitofp_4i32_to_2f64
; SSE41-LABEL: uitofp_4i32_to_2f64:
; SSE41: # %bb.0:
; SSE41-NEXT: pxor %xmm1, %xmm1
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE41-NEXT: psrld $16, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
@@ -940,17 +940,18 @@ define <4 x double> @uitofp_4i32_to_4f64
; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE2-NEXT: movapd {{.*#+}} xmm2 = [6.5536E+4,6.5536E+4]
; SSE2-NEXT: mulpd %xmm2, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [65535,0,65535,0,0,0,0,0]
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
+; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: addpd %xmm1, %xmm0
-; SSE2-NEXT: movdqa %xmm3, %xmm1
+; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: psrld $16, %xmm1
-; SSE2-NEXT: cvtdq2pd %xmm1, %xmm4
-; SSE2-NEXT: mulpd %xmm2, %xmm4
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
-; SSE2-NEXT: cvtdq2pd %xmm3, %xmm1
-; SSE2-NEXT: addpd %xmm4, %xmm1
+; SSE2-NEXT: cvtdq2pd %xmm1, %xmm5
+; SSE2-NEXT: mulpd %xmm2, %xmm5
+; SSE2-NEXT: pand %xmm3, %xmm4
+; SSE2-NEXT: cvtdq2pd %xmm4, %xmm1
+; SSE2-NEXT: addpd %xmm5, %xmm1
; SSE2-NEXT: retq
;
; SSE41-LABEL: uitofp_4i32_to_4f64:
@@ -962,15 +963,16 @@ define <4 x double> @uitofp_4i32_to_4f64
; SSE41-NEXT: mulpd %xmm2, %xmm1
; SSE41-NEXT: pxor %xmm3, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4],xmm3[5],xmm0[6],xmm3[7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-NEXT: addpd %xmm1, %xmm0
-; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3,4,5,6,7]
-; SSE41-NEXT: psrld $16, %xmm4
-; SSE41-NEXT: cvtdq2pd %xmm4, %xmm4
-; SSE41-NEXT: mulpd %xmm2, %xmm4
-; SSE41-NEXT: cvtdq2pd %xmm3, %xmm1
-; SSE41-NEXT: addpd %xmm4, %xmm1
+; SSE41-NEXT: movdqa %xmm4, %xmm1
+; SSE41-NEXT: psrld $16, %xmm1
+; SSE41-NEXT: cvtdq2pd %xmm1, %xmm5
+; SSE41-NEXT: mulpd %xmm2, %xmm5
+; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0],xmm3[1],xmm4[2],xmm3[3],xmm4[4,5,6,7]
+; SSE41-NEXT: cvtdq2pd %xmm4, %xmm1
+; SSE41-NEXT: addpd %xmm5, %xmm1
; SSE41-NEXT: retq
;
; AVX1-LABEL: uitofp_4i32_to_4f64:
@@ -3508,7 +3510,7 @@ define <2 x double> @uitofp_load_2i32_to
; SSE41: # %bb.0:
; SSE41-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE41-NEXT: pxor %xmm1, %xmm1
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE41-NEXT: psrld $16, %xmm0
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
@@ -3520,7 +3522,7 @@ define <2 x double> @uitofp_load_2i32_to
; VEX: # %bb.0:
; VEX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; VEX-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3,4,5,6,7]
+; VEX-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4,5,6,7]
; VEX-NEXT: vcvtdq2pd %xmm1, %xmm1
; VEX-NEXT: vpsrld $16, %xmm0, %xmm0
; VEX-NEXT: vcvtdq2pd %xmm0, %xmm0
@@ -3742,17 +3744,18 @@ define <4 x double> @uitofp_load_4i32_to
; SSE2-NEXT: cvtdq2pd %xmm1, %xmm1
; SSE2-NEXT: movapd {{.*#+}} xmm2 = [6.5536E+4,6.5536E+4]
; SSE2-NEXT: mulpd %xmm2, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
+; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [65535,0,65535,0,0,0,0,0]
+; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
+; SSE2-NEXT: pand %xmm3, %xmm0
; SSE2-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE2-NEXT: addpd %xmm1, %xmm0
-; SSE2-NEXT: movdqa %xmm3, %xmm1
+; SSE2-NEXT: movdqa %xmm4, %xmm1
; SSE2-NEXT: psrld $16, %xmm1
-; SSE2-NEXT: cvtdq2pd %xmm1, %xmm4
-; SSE2-NEXT: mulpd %xmm2, %xmm4
-; SSE2-NEXT: pand {{.*}}(%rip), %xmm3
-; SSE2-NEXT: cvtdq2pd %xmm3, %xmm1
-; SSE2-NEXT: addpd %xmm4, %xmm1
+; SSE2-NEXT: cvtdq2pd %xmm1, %xmm5
+; SSE2-NEXT: mulpd %xmm2, %xmm5
+; SSE2-NEXT: pand %xmm3, %xmm4
+; SSE2-NEXT: cvtdq2pd %xmm4, %xmm1
+; SSE2-NEXT: addpd %xmm5, %xmm1
; SSE2-NEXT: retq
;
; SSE41-LABEL: uitofp_load_4i32_to_4f64:
@@ -3765,15 +3768,16 @@ define <4 x double> @uitofp_load_4i32_to
; SSE41-NEXT: mulpd %xmm2, %xmm1
; SSE41-NEXT: pxor %xmm3, %xmm3
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[2,3,0,1]
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4],xmm3[5],xmm0[6],xmm3[7]
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1],xmm0[2],xmm3[3],xmm0[4,5,6,7]
; SSE41-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-NEXT: addpd %xmm1, %xmm0
-; SSE41-NEXT: pblendw {{.*#+}} xmm3 = xmm4[0],xmm3[1],xmm4[2],xmm3[3,4,5,6,7]
-; SSE41-NEXT: psrld $16, %xmm4
-; SSE41-NEXT: cvtdq2pd %xmm4, %xmm4
-; SSE41-NEXT: mulpd %xmm2, %xmm4
-; SSE41-NEXT: cvtdq2pd %xmm3, %xmm1
-; SSE41-NEXT: addpd %xmm4, %xmm1
+; SSE41-NEXT: movdqa %xmm4, %xmm1
+; SSE41-NEXT: psrld $16, %xmm1
+; SSE41-NEXT: cvtdq2pd %xmm1, %xmm5
+; SSE41-NEXT: mulpd %xmm2, %xmm5
+; SSE41-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0],xmm3[1],xmm4[2],xmm3[3],xmm4[4,5,6,7]
+; SSE41-NEXT: cvtdq2pd %xmm4, %xmm1
+; SSE41-NEXT: addpd %xmm5, %xmm1
; SSE41-NEXT: retq
;
; AVX1-LABEL: uitofp_load_4i32_to_4f64:
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