[PATCH] D54467: [X86] Disable combineToExtendVectorInReg under -x86-experimental-vector-widening-legalization. Add custom type legalization for extends.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM with one minor and the followup fix for aggregate_sitofp_8i16_to_8f32



================
Comment at: lib/Target/X86/X86ISelLowering.cpp:26319
+    EVT InVT = In.getValueType();
+    assert((VT == MVT::v16i32 || VT == MVT::v8i64) && "Unexpected VT!");
+    if (InVT.is128BitVector()) {
----------------
Move the assert directly after EVT VT.


https://reviews.llvm.org/D54467