[PATCH] D54623: [MSP430] Optimize srl/sra in case of A >> (8 + N)

[Anton Korobeynikov via Phabricator via llvm-commits]

asl requested changes to this revision.
asl added inline comments.
This revision now requires changes to proceed.


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Comment at: lib/Target/MSP430/MSP430ISelLowering.cpp:954
+    unsigned ExtOpc =
+        Opc == ISD::SRA ? ISD::SIGN_EXTEND_INREG : ISD::ZERO_EXTEND;
+    Victim = DAG.getNode(ExtOpc, dl, VT, Victim, DAG.getValueType(MVT::i8));
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efriedma wrote:
> I'm confused how the ZERO_EXTEND case works; you aren't even passing the right number of operands for a ZERO_EXTEND.  (There is no ZERO_EXTEND_INREG because it's equivalent to an AND with the appropriate immediate.  There's a helper function SelectionDAG::getZeroExtendInReg() to generate that for you.)
Oh, you're right. It works here because the type operand for zext is essentially ignored and there is only a single version of i8 => i16 zext to match.


Repository:
  rL LLVM

https://reviews.llvm.org/D54623