[PATCH] D54609: AArch64: Emit a call frame instruction for the shadow call stack register.

[Peter Collingbourne via Phabricator via llvm-commits]

pcc updated this revision to Diff 174402.
pcc added a comment.

Rebase


Repository:
  rL LLVM

https://reviews.llvm.org/D54609

Files:
  llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
  llvm/test/CodeGen/AArch64/shadow-call-stack.ll


Index: llvm/test/CodeGen/AArch64/shadow-call-stack.ll
===================================================================
--- llvm/test/CodeGen/AArch64/shadow-call-stack.ll
+++ llvm/test/CodeGen/AArch64/shadow-call-stack.ll
@@ -22,6 +22,7 @@
 define i32 @f3() shadowcallstack {
   ; CHECK: f3:
   ; CHECK: str x30, [x18], #8
+  ; CHECK: .cfi_escape 0x16, 0x12, 0x02, 0x82, 0x78
   ; CHECK: str x30, [sp, #-16]!
   %res = call i32 @bar()
   %res1 = add i32 %res, 1
Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -590,10 +590,12 @@
     const DebugLoc &DL, const TargetInstrInfo *TII, int CSStackSizeInc,
     bool NeedsWinCFI, bool InProlog = true) {
   // Ignore instructions that do not operate on SP, i.e. shadow call stack
-  // instructions.
+  // instructions and associated CFI instruction.
   while (MBBI->getOpcode() == AArch64::STRXpost ||
-         MBBI->getOpcode() == AArch64::LDRXpre) {
-    assert(MBBI->getOperand(0).getReg() != AArch64::SP);
+         MBBI->getOpcode() == AArch64::LDRXpre ||
+         MBBI->getOpcode() == AArch64::CFI_INSTRUCTION) {
+    if (MBBI->getOpcode() != AArch64::CFI_INSTRUCTION)
+      assert(MBBI->getOperand(0).getReg() != AArch64::SP);
     ++MBBI;
   }
   unsigned NewOpc;
@@ -690,9 +692,11 @@
   unsigned Opc = MI.getOpcode();
 
   // Ignore instructions that do not operate on SP, i.e. shadow call stack
-  // instructions.
-  if (Opc == AArch64::STRXpost || Opc == AArch64::LDRXpre) {
-    assert(MI.getOperand(0).getReg() != AArch64::SP);
+  // instructions and associated CFI instruction.
+  if (Opc == AArch64::STRXpost || Opc == AArch64::LDRXpre ||
+      Opc == AArch64::CFI_INSTRUCTION) {
+    if (Opc != AArch64::CFI_INSTRUCTION)
+      assert(MI.getOperand(0).getReg() != AArch64::SP);
     return;
   }
 
@@ -1729,6 +1733,21 @@
       BuildMI(MBB, MI, DL, TII.get(AArch64::SEH_Nop))
           .setMIFlag(MachineInstr::FrameSetup);
 
+    // Emit a CFI instruction that causes 8 to be subtracted from the value of
+    // x18 when unwinding past this frame.
+    static const char CFIInst[] = {
+        dwarf::DW_CFA_val_expression,
+        18, // register
+        2,  // length
+        static_cast<char>(dwarf::DW_OP_breg18),
+        static_cast<char>(-8) & 0x7f, // addend (sleb128)
+    };
+    unsigned CFIIndex =
+        MF.addFrameInst(MCCFIInstruction::createEscape(nullptr, CFIInst));
+    BuildMI(MBB, MI, DL, TII.get(AArch64::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex)
+        .setMIFlag(MachineInstr::FrameSetup);
+
     // This instruction also makes x18 live-in to the entry block.
     MBB.addLiveIn(AArch64::X18);
   }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D54609.174402.patch
Type: text/x-patch
Size: 2795 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181116/db4b3f94/attachment.bin>