[PATCH] D54467: [X86] Disable combineToExtendVectorInReg under -x86-experimental-vector-widening-legalization. Add custom type legalization for extends.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:26247
+    assert((VT == MVT::v16i32 || VT == MVT::v8i64) && "Unexpected VT!");
+    if (In.getValueType().getSizeInBits() == 128) {
+      // Perform custom splitting instead of the two stage extend we would get
----------------
Use is128BitVector() ?


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Comment at: lib/Target/X86/X86ISelLowering.cpp:26263
+      unsigned NumElts = InVT.getVectorNumElements();
+      unsigned HalfNumElts = InVT.getVectorNumElements() / 2;
+      SmallVector<int, 16> ShufMask(NumElts, -1);
----------------
 NumElts / 2


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:26264
+      unsigned HalfNumElts = InVT.getVectorNumElements() / 2;
+      SmallVector<int, 16> ShufMask(NumElts, -1);
+      for (unsigned i = 0; i != HalfNumElts; ++i)
----------------
Use SM_SentinelUndef instead of -1


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:26269
+      SDValue Hi = DAG.getVectorShuffle(InVT, dl, In, In, ShufMask);
+      Hi = DAG.getNode(InRegOpc, dl, HiVT, Hi);
+
----------------
Worth using getExtendInVec ?


https://reviews.llvm.org/D54467