[PATCH] D54561: [WebAssembly] Renumber SIMD bitwise instructions

[Thomas Lively via Phabricator via llvm-commits]

tlively created this revision.
tlively added a reviewer: aheejin.
Herald added subscribers: llvm-commits, sunfish, jgravelle-google, sbc100, dschuff.

Changed to match https://github.com/WebAssembly/simd/pull/54.


Repository:
  rL LLVM

https://reviews.llvm.org/D54561

Files:
  lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  test/MC/WebAssembly/simd-encodings.s


Index: test/MC/WebAssembly/simd-encodings.s
===================================================================
--- test/MC/WebAssembly/simd-encodings.s
+++ test/MC/WebAssembly/simd-encodings.s
@@ -226,18 +226,18 @@
     # CHECK: f64x2.ge # encoding: [0xfd,0x4b]
     f64x2.ge
 
-    # CHECK: v128.and # encoding: [0xfd,0x4c]
+    # CHECK: v128.not # encoding: [0xfd,0x4c]
+    v128.not
+
+    # CHECK: v128.and # encoding: [0xfd,0x4d]
     v128.and
 
-    # CHECK: v128.or # encoding: [0xfd,0x4d]
+    # CHECK: v128.or # encoding: [0xfd,0x4e]
     v128.or
 
-    # CHECK: v128.xor # encoding: [0xfd,0x4e]
+    # CHECK: v128.xor # encoding: [0xfd,0x4f]
     v128.xor
 
-    # CHECK: v128.not # encoding: [0xfd,0x4f]
-    v128.not
-
     # CHECK: v128.bitselect # encoding: [0xfd,0x50]
     v128.bitselect
 
Index: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===================================================================
--- lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -559,17 +559,17 @@
                         vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
 }
 
+// Bitwise logic: v128.not
+foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
+defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 76>;
+
 // Bitwise logic: v128.and / v128.or / v128.xor
 let isCommutable = 1 in {
-defm AND : SIMDBitwise<and, "and", 76>;
-defm OR : SIMDBitwise<or, "or", 77>;
-defm XOR : SIMDBitwise<xor, "xor", 78>;
+defm AND : SIMDBitwise<and, "and", 77>;
+defm OR : SIMDBitwise<or, "or", 78>;
+defm XOR : SIMDBitwise<xor, "xor", 79>;
 } // isCommutable = 1
 
-// Bitwise logic: v128.not
-foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
-defm NOT: SIMDUnary<vec_t, "v128", vnot, "not", 79>;
-
 // Bitwise select: v128.bitselect
 foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
   defm BITSELECT_#vec_t :


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