[llvm] r346894 - Bias physical register immediate assignments
Nirav Dave via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 14 13:11:54 PST 2018
Author: niravd
Date: Wed Nov 14 13:11:53 2018
New Revision: 346894
URL: http://llvm.org/viewvc/llvm-project?rev=346894&view=rev
Log:
Bias physical register immediate assignments
The machine scheduler currently biases register copies to/from
physical registers to be closer to their point of use / def to
minimize their live ranges. This change extends this to also physical
register assignments from immediate values.
This causes a reduction in reduction in overall register pressure and
minor reduction in spills and indirectly fixes an out-of-registers
assertion (PR39391).
Most test changes are from minor instruction reorderings and register
name selection changes and direct consequences of that.
Reviewers: MatzeB, qcolombet, myatsina, pcc
Subscribers: nemanjai, jvesely, nhaehnle, eraman, hiraditya,
javed.absar, arphaman, jfb, jsji, llvm-commits
Differential Revision: https://reviews.llvm.org/D54218
Added:
llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll
Modified:
llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
llvm/trunk/lib/CodeGen/MachineScheduler.cpp
llvm/trunk/lib/Target/X86/X86InstrCompiler.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll
llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll
llvm/trunk/test/CodeGen/AMDGPU/local-atomics64.ll
llvm/trunk/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
llvm/trunk/test/CodeGen/AMDGPU/ret.ll
llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
llvm/trunk/test/CodeGen/X86/anyext.ll
llvm/trunk/test/CodeGen/X86/atomic_mi.ll
llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll
llvm/trunk/test/CodeGen/X86/bss_pagealigned.ll
llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll
llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll
llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll
llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll
llvm/trunk/test/CodeGen/X86/code-model-elf-memset.ll
llvm/trunk/test/CodeGen/X86/combine-srem.ll
llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
llvm/trunk/test/CodeGen/X86/divrem.ll
llvm/trunk/test/CodeGen/X86/known-bits.ll
llvm/trunk/test/CodeGen/X86/machine-cse.ll
llvm/trunk/test/CodeGen/X86/memset-nonzero.ll
llvm/trunk/test/CodeGen/X86/misched-code-difference-with-debug.ll
llvm/trunk/test/CodeGen/X86/patchpoint.ll
llvm/trunk/test/CodeGen/X86/pr32282.ll
llvm/trunk/test/CodeGen/X86/pr36865.ll
llvm/trunk/test/CodeGen/X86/pr38865.ll
llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll
llvm/trunk/test/CodeGen/X86/shrink_vmul-widen.ll
llvm/trunk/test/CodeGen/X86/shrink_vmul.ll
llvm/trunk/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
llvm/trunk/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll
llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll
llvm/trunk/test/CodeGen/X86/vector-idiv-v2i32.ll
llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll
llvm/trunk/test/DebugInfo/X86/live-debug-values.ll
Modified: llvm/trunk/include/llvm/CodeGen/MachineScheduler.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineScheduler.h?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineScheduler.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineScheduler.h Wed Nov 14 13:11:53 2018
@@ -794,7 +794,7 @@ public:
/// Represent the type of SchedCandidate found within a single queue.
/// pickNodeBidirectional depends on these listed by decreasing priority.
enum CandReason : uint8_t {
- NoCand, Only1, PhysRegCopy, RegExcess, RegCritical, Stall, Cluster, Weak,
+ NoCand, Only1, PhysReg, RegExcess, RegCritical, Stall, Cluster, Weak,
RegMax, ResourceReduce, ResourceDemand, BotHeightReduce, BotPathReduce,
TopDepthReduce, TopPathReduce, NextDefUse, NodeOrder};
@@ -928,7 +928,7 @@ bool tryPressure(const PressureChange &T
const TargetRegisterInfo *TRI,
const MachineFunction &MF);
unsigned getWeakLeft(const SUnit *SU, bool isTop);
-int biasPhysRegCopy(const SUnit *SU, bool isTop);
+int biasPhysReg(const SUnit *SU, bool isTop);
/// GenericScheduler shrinks the unscheduled zone using heuristics to balance
/// the schedule.
@@ -1006,7 +1006,7 @@ protected:
const RegPressureTracker &RPTracker,
SchedCandidate &Candidate);
- void reschedulePhysRegCopies(SUnit *SU, bool isTop);
+ void reschedulePhysReg(SUnit *SU, bool isTop);
};
/// PostGenericScheduler - Interface to the scheduling algorithm used by
Modified: llvm/trunk/lib/CodeGen/MachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineScheduler.cpp?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineScheduler.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineScheduler.cpp Wed Nov 14 13:11:53 2018
@@ -2516,7 +2516,7 @@ const char *GenericSchedulerBase::getRea
switch (Reason) {
case NoCand: return "NOCAND ";
case Only1: return "ONLY1 ";
- case PhysRegCopy: return "PREG-COPY ";
+ case PhysReg: return "PHYS-REG ";
case RegExcess: return "REG-EXCESS";
case RegCritical: return "REG-CRIT ";
case Stall: return "STALL ";
@@ -2852,24 +2852,41 @@ unsigned getWeakLeft(const SUnit *SU, bo
/// copies which can be prescheduled. The rest (e.g. x86 MUL) could be bundled
/// with the operation that produces or consumes the physreg. We'll do this when
/// regalloc has support for parallel copies.
-int biasPhysRegCopy(const SUnit *SU, bool isTop) {
+int biasPhysReg(const SUnit *SU, bool isTop) {
const MachineInstr *MI = SU->getInstr();
- if (!MI->isCopy())
- return 0;
- unsigned ScheduledOper = isTop ? 1 : 0;
- unsigned UnscheduledOper = isTop ? 0 : 1;
- // If we have already scheduled the physreg produce/consumer, immediately
- // schedule the copy.
- if (TargetRegisterInfo::isPhysicalRegister(
- MI->getOperand(ScheduledOper).getReg()))
- return 1;
- // If the physreg is at the boundary, defer it. Otherwise schedule it
- // immediately to free the dependent. We can hoist the copy later.
- bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
- if (TargetRegisterInfo::isPhysicalRegister(
- MI->getOperand(UnscheduledOper).getReg()))
- return AtBoundary ? -1 : 1;
+ if (MI->isCopy()) {
+ unsigned ScheduledOper = isTop ? 1 : 0;
+ unsigned UnscheduledOper = isTop ? 0 : 1;
+ // If we have already scheduled the physreg produce/consumer, immediately
+ // schedule the copy.
+ if (TargetRegisterInfo::isPhysicalRegister(
+ MI->getOperand(ScheduledOper).getReg()))
+ return 1;
+ // If the physreg is at the boundary, defer it. Otherwise schedule it
+ // immediately to free the dependent. We can hoist the copy later.
+ bool AtBoundary = isTop ? !SU->NumSuccsLeft : !SU->NumPredsLeft;
+ if (TargetRegisterInfo::isPhysicalRegister(
+ MI->getOperand(UnscheduledOper).getReg()))
+ return AtBoundary ? -1 : 1;
+ }
+
+ if (MI->isMoveImmediate()) {
+ // If we have a move immediate and all successors have been assigned, bias
+ // towards scheduling this later. Make sure all register defs are to
+ // physical registers.
+ bool DoBias = true;
+ for (const MachineOperand &Op : MI->defs()) {
+ if (Op.isReg() && !TargetRegisterInfo::isPhysicalRegister(Op.getReg())) {
+ DoBias = false;
+ break;
+ }
+ }
+
+ if (DoBias)
+ return isTop ? -1 : 1;
+ }
+
return 0;
}
} // end namespace llvm
@@ -2930,9 +2947,9 @@ void GenericScheduler::tryCandidate(Sche
return;
}
- if (tryGreater(biasPhysRegCopy(TryCand.SU, TryCand.AtTop),
- biasPhysRegCopy(Cand.SU, Cand.AtTop),
- TryCand, Cand, PhysRegCopy))
+ // Bias PhysReg Defs and copies to their uses and defined respectively.
+ if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop),
+ biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg))
return;
// Avoid exceeding the target's limit.
@@ -3179,7 +3196,7 @@ SUnit *GenericScheduler::pickNode(bool &
return SU;
}
-void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
+void GenericScheduler::reschedulePhysReg(SUnit *SU, bool isTop) {
MachineBasicBlock::iterator InsertPos = SU->getInstr();
if (!isTop)
++InsertPos;
@@ -3194,7 +3211,7 @@ void GenericScheduler::reschedulePhysReg
if (isTop ? DepSU->Succs.size() > 1 : DepSU->Preds.size() > 1)
continue;
MachineInstr *Copy = DepSU->getInstr();
- if (!Copy->isCopy())
+ if (!Copy->isCopy() && !Copy->isMoveImmediate())
continue;
LLVM_DEBUG(dbgs() << " Rescheduling physreg copy ";
DAG->dumpNode(*Dep.getSUnit()));
@@ -3208,18 +3225,18 @@ void GenericScheduler::reschedulePhysReg
/// does.
///
/// FIXME: Eventually, we may bundle physreg copies rather than rescheduling
-/// them here. See comments in biasPhysRegCopy.
+/// them here. See comments in biasPhysReg.
void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
if (IsTopNode) {
SU->TopReadyCycle = std::max(SU->TopReadyCycle, Top.getCurrCycle());
Top.bumpNode(SU);
if (SU->hasPhysRegUses)
- reschedulePhysRegCopies(SU, true);
+ reschedulePhysReg(SU, true);
} else {
SU->BotReadyCycle = std::max(SU->BotReadyCycle, Bot.getCurrCycle());
Bot.bumpNode(SU);
if (SU->hasPhysRegDefs)
- reschedulePhysRegCopies(SU, false);
+ reschedulePhysReg(SU, false);
}
}
Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Wed Nov 14 13:11:53 2018
@@ -143,7 +143,7 @@ def WIN_ALLOCA_64 : I<0, Pseudo, (outs),
// These instructions XOR the frame pointer into a GPR. They are used in some
// stack protection schemes. These are post-RA pseudos because we only know the
// frame register after register allocation.
-let Constraints = "$src = $dst", isPseudo = 1, Defs = [EFLAGS] in {
+let Constraints = "$src = $dst", isMoveImm = 1, isPseudo = 1, Defs = [EFLAGS] in {
def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
"xorl\t$$FP, $src", []>,
Requires<[NotLP64]>, Sched<[WriteALU]>;
@@ -270,7 +270,7 @@ def MORESTACK_RET_RESTORE_R10 : I<0, Pse
// Alias instruction mapping movr0 to xor.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
- isPseudo = 1, AddedComplexity = 10 in
+ isPseudo = 1, isMoveImm = 1, AddedComplexity = 10 in
def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
[(set GR32:$dst, 0)]>, Sched<[WriteZero]>;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Nov 14 13:11:53 2018
@@ -1493,7 +1493,7 @@ def MOV64rr : RI<0x89, MRMDestReg, (outs
"mov{q}\t{$src, $dst|$dst, $src}", []>;
}
-let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
"mov{b}\t{$src, $dst|$dst, $src}",
[(set GR8:$dst, imm:$src)]>;
@@ -1507,7 +1507,7 @@ def MOV64ri32 : RIi32S<0xC7, MRM0r, (out
"mov{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, i64immSExt32:$src)]>;
}
-let isReMaterializable = 1 in {
+let isReMaterializable = 1, isMoveImm = 1 in {
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
"movabs{q}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, relocImm:$src)]>;
Modified: llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/call-argument-types.ll Wed Nov 14 13:11:53 2018
@@ -61,11 +61,11 @@ declare void @external_void_func_v16i8(<
; MESA-DAG: s_mov_b64 s[0:1], s[36:37]
-; GCN: v_mov_b32_e32 v0, 1{{$}}
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1 at rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1 at rel32@hi+4
+; GCN-DAG: v_mov_b32_e32 v0, 1{{$}}
; MESA-DAG: s_mov_b64 s[2:3], s[38:39]
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1 at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1 at rel32@hi+4
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm
@@ -123,12 +123,12 @@ define amdgpu_kernel void @test_call_ext
; GCN-LABEL: {{^}}test_call_external_void_func_i8_imm:
; MESA-DAG: s_mov_b32 s33, s3{{$}}
-; GCN: v_mov_b32_e32 v0, 0x7b
-; HSA-DAG: s_mov_b32 s4, s33{{$}}
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8 at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8 at rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8 at rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8 at rel32@hi+4
+; GCN-DAG: v_mov_b32_e32 v0, 0x7b
+; HSA-DAG: s_mov_b32 s4, s33{{$}}
; GCN-DAG: s_mov_b32 s32, s33{{$}}
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
@@ -144,11 +144,11 @@ define amdgpu_kernel void @test_call_ext
; MESA-DAG: s_mov_b32 s33, s3{{$}}
; GCN-DAG: buffer_load_sbyte v0
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_signext at rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_signext at rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_signext at rel32@hi+4
+; GCN-DAG: s_mov_b32 s4, s33
; GCN-DAG: s_mov_b32 s32, s3
; GCN: s_waitcnt vmcnt(0)
@@ -165,10 +165,9 @@ define amdgpu_kernel void @test_call_ext
; HSA-DAG: s_mov_b32 s33, s9{{$}}
; GCN-DAG: buffer_load_ubyte v0
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_zeroext at rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i8_zeroext at rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i8_zeroext at rel32@hi+4
; GCN-DAG: s_mov_b32 s32, s33
@@ -197,10 +196,9 @@ define amdgpu_kernel void @test_call_ext
; MESA-DAG: s_mov_b32 s33, s3{{$}}
; GCN-DAG: buffer_load_sshort v0
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_signext at rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_signext at rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_signext at rel32@hi+4
; GCN-DAG: s_mov_b32 s32, s33
@@ -217,11 +215,9 @@ define amdgpu_kernel void @test_call_ext
; MESA-DAG: s_mov_b32 s33, s3{{$}}
-; GCN-DAG: buffer_load_ushort v0
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_zeroext at rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i16_zeroext at rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i16_zeroext at rel32@hi+4
; GCN-DAG: s_mov_b32 s32, s33
@@ -237,11 +233,11 @@ define amdgpu_kernel void @test_call_ext
; GCN-LABEL: {{^}}test_call_external_void_func_i32_imm:
; MESA-DAG: s_mov_b32 s33, s3{{$}}
-; GCN: v_mov_b32_e32 v0, 42
-; GCN: s_mov_b32 s4, s33
-; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
-; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i32 at rel32@lo+4
-; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i32 at rel32@hi+4
+; GCN-DAG: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
+; GCN-DAG: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i32 at rel32@lo+4
+; GCN-DAG: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i32 at rel32@hi+4
+; GCN-DAG: v_mov_b32_e32 v0, 42
+; GCN-DAG: s_mov_b32 s4, s33
; GCN-DAG: s_mov_b32 s32, s33
; GCN: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
@@ -688,7 +684,7 @@ define amdgpu_kernel void @test_call_ext
; GCN-NOT: s_add_u32 [[SP]]
; GCN-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:4
; GCN-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s{{\[[0-9]+:[0-9]+\]}}, [[SP]] offset:8
-; GCN-NEXT: s_swappc_b64
+; GCN: s_swappc_b64
; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:16
; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:20
; GCN-NOT: s_sub_u32 [[SP]]
Modified: llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll Wed Nov 14 13:11:53 2018
@@ -383,13 +383,12 @@ define void @other_arg_use_workgroup_id_
; GCN: enable_sgpr_workgroup_id_y = 0
; GCN: enable_sgpr_workgroup_id_z = 0
+; GCN-NOT: s6
; GCN-DAG: s_mov_b32 s33, s7
; GCN-DAG: v_mov_b32_e32 v0, 0x22b
-
-; GCN-NOT: s6
-; GCN: s_mov_b32 s4, s33
-; GCN-NOT: s6
+; GCN-DAG: s_mov_b32 s4, s33
; GCN-DAG: s_mov_b32 s32, s33
+; GCN-NOT: s6
; GCN: s_swappc_b64
define amdgpu_kernel void @kern_indirect_other_arg_use_workgroup_id_x() #1 {
call void @other_arg_use_workgroup_id_x(i32 555)
@@ -578,16 +577,16 @@ define void @func_use_every_sgpr_input_c
; GCN: s_swappc_b64
-; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:4
-; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], s[[LO_X]]
-; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], s[[HI_X]]
-; GCN: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
-; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], s[[LO_Y]]
-; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], s[[HI_Y]]
-; GCN: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
-; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], s[[LO_Z]]
-; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], s[[HI_Z]]
-; GCN: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
+; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:4
+; GCN-DAG: v_mov_b32_e32 v[[LO1:[0-9]+]], s[[LO_X]]
+; GCN-DAG: v_mov_b32_e32 v[[HI1:[0-9]+]], s[[HI_X]]
+; GCN-DAG: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO1]]:[[HI1]]{{\]}}
+; GCN-DAG: v_mov_b32_e32 v[[LO2:[0-9]+]], s[[LO_Y]]
+; GCN-DAG: v_mov_b32_e32 v[[HI2:[0-9]+]], s[[HI_Y]]
+; GCN-DAG: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO2]]:[[HI2]]{{\]}}
+; GCN-DAG: v_mov_b32_e32 v[[LO3:[0-9]+]], s[[LO_Z]]
+; GCN-DAG: v_mov_b32_e32 v[[HI3:[0-9]+]], s[[HI_Z]]
+; GCN-DAG: {{flat|global}}_load_dword v{{[0-9]+}}, v{{\[}}[[LO3]]:[[HI3]]{{\]}}
; GCN: ; use
; GCN: ; use [[SAVE_X]]
; GCN: ; use [[SAVE_Y]]
Modified: llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/frame-index-elimination.ll Wed Nov 14 13:11:53 2018
@@ -167,13 +167,13 @@ ret:
; GCN-DAG: s_movk_i32 s6, 0x204
; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
-; CI: v_add_i32_e64 v0, s[6:7], s6, [[SCALED]]
+; CI: v_add_i32_e64 [[VZ:v[0-9]+]], s[6:7], s6, [[SCALED]]
; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
-; GFX9: v_add_u32_e32 v0, s6, [[SCALED]]
+; GFX9: v_add_u32_e32 [[VZ:v[0-9]+]], s6, [[SCALED]]
-; GCN: v_mul_lo_i32 v0, v0, 9
-; GCN: ds_write_b32 v0, v0
+; GCN: v_mul_lo_i32 [[VZ]], [[VZ]], 9
+; GCN: ds_write_b32 v0, [[VZ]]
define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
%alloca0 = alloca [128 x i32], align 4, addrspace(5)
%alloca1 = alloca [8 x i32], align 4, addrspace(5)
@@ -191,13 +191,13 @@ define void @func_other_fi_user_non_inli
; GCN-DAG: s_movk_i32 [[OFFSET:s[0-9]+]], 0x204
; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[DIFF]], 6
-; CI: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]]
+; CI: v_add_i32_e64 [[VZ:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]]
; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]
-; GFX9: v_add_u32_e32 v0, [[OFFSET]], [[SCALED]]
+; GFX9: v_add_u32_e32 [[VZ:v[0-9]+]], [[OFFSET]], [[SCALED]]
-; GCN: v_mul_lo_i32 v0, v0, 9
-; GCN: ds_write_b32 v0, v0
+; GCN: v_mul_lo_i32 [[VZ]], [[VZ]], 9
+; GCN: ds_write_b32 v0, [[VZ]]
define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 {
%alloca0 = alloca [128 x i32], align 4, addrspace(5)
%alloca1 = alloca [8 x i32], align 4, addrspace(5)
Modified: llvm/trunk/test/CodeGen/AMDGPU/local-atomics64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/local-atomics64.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/local-atomics64.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/local-atomics64.ll Wed Nov 14 13:11:53 2018
@@ -364,7 +364,7 @@ define amdgpu_kernel void @lds_atomic_ad
; GFX89-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24
; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9
; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0
-; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
+; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GCN: ds_add_u64 {{v[0-9]+}}, v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32
; GCN: s_endpgm
define amdgpu_kernel void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind {
Modified: llvm/trunk/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/multi-divergent-exit-region.ll Wed Nov 14 13:11:53 2018
@@ -60,11 +60,11 @@
; GCN-LABEL: {{^}}multi_divergent_region_exit_ret_ret:
-; GCN: s_mov_b64 [[EXIT1:s\[[0-9]+:[0-9]+\]]], 0
-; GCN: v_cmp_lt_i32_e32 vcc, 1,
-; GCN: s_mov_b64 [[EXIT0:s\[[0-9]+:[0-9]+\]]], 0
-; GCN: s_and_saveexec_b64
-; GCN: s_xor_b64
+; GCN-DAG: s_mov_b64 [[EXIT1:s\[[0-9]+:[0-9]+\]]], 0
+; GCN-DAG: v_cmp_lt_i32_e32 vcc, 1,
+; GCN-DAG: s_mov_b64 [[EXIT0:s\[[0-9]+:[0-9]+\]]], 0
+; GCN-DAG: s_and_saveexec_b64
+; GCN-DAG: s_xor_b64
; GCN: ; %LeafBlock1
; GCN-NEXT: s_mov_b64 [[EXIT0]], exec
@@ -92,8 +92,8 @@
; GCN-NEXT: s_xor_b64
; GCN: ; %exit1
-; GCN: ds_write_b32
-; GCN: s_andn2_b64 [[EXIT0]], [[EXIT0]], exec
+; GCN-DAG: ds_write_b32
+; GCN-DAG: s_andn2_b64 [[EXIT0]], [[EXIT0]], exec
; GCN: ; %Flow5
; GCN-NEXT: s_or_b64 exec, exec,
Modified: llvm/trunk/test/CodeGen/AMDGPU/ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/ret.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/ret.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/ret.ll Wed Nov 14 13:11:53 2018
@@ -17,14 +17,13 @@ bb:
}
; GCN-LABEL: {{^}}vgpr_literal:
-; GCN: v_mov_b32_e32 v4, v0
-; GCN: exp mrt0 v4, v4, v4, v4 done vm
+; GCN: exp mrt0 v0, v0, v0, v0 done vm
; GCN-DAG: v_mov_b32_e32 v0, 1.0
; GCN-DAG: v_mov_b32_e32 v1, 2.0
; GCN-DAG: v_mov_b32_e32 v2, 4.0
; GCN-DAG: v_mov_b32_e32 v3, -1.0
-; GCN: s_waitcnt expcnt(0)
+; GCN-DAG: s_waitcnt expcnt(0)
; GCN-NOT: s_endpgm
define amdgpu_vs { float, float, float, float } @vgpr_literal([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb:
@@ -226,15 +225,14 @@ bb:
}
; GCN-LABEL: {{^}}structure_literal:
-; GCN: v_mov_b32_e32 v3, v0
-; GCN: exp mrt0 v3, v3, v3, v3 done vm
+; GCN: exp mrt0 v0, v0, v0, v0 done vm
; GCN-DAG: v_mov_b32_e32 v0, 1.0
; GCN-DAG: s_mov_b32 s0, 2
; GCN-DAG: s_mov_b32 s1, 3
; GCN-DAG: v_mov_b32_e32 v1, 2.0
; GCN-DAG: v_mov_b32_e32 v2, 4.0
-; GCN: s_waitcnt expcnt(0)
+; GCN-DAG: s_waitcnt expcnt(0)
define amdgpu_vs { { float, i32 }, { i32, <2 x float> } } @structure_literal([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
Modified: llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll Wed Nov 14 13:11:53 2018
@@ -40,9 +40,9 @@ define %struct.__vv* @t(%struct.Key* %de
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq _xxGetOffsetForCode
+; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: movq %rbx, %rdi
; CHECK-NEXT: callq _xxCalculateMidType
; CHECK-NEXT: cmpl $1, %eax
; CHECK-NEXT: jne LBB0_1
Modified: llvm/trunk/test/CodeGen/X86/anyext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/anyext.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/anyext.ll (original)
+++ llvm/trunk/test/CodeGen/X86/anyext.ll Wed Nov 14 13:11:53 2018
@@ -42,8 +42,8 @@ define i32 @bar(i32 %p, i16 zeroext %x)
; X64-LABEL: bar:
; X64: # %bb.0:
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divw %si
; X64-NEXT: # kill: def $ax killed $ax def $eax
; X64-NEXT: andl $1, %eax
Modified: llvm/trunk/test/CodeGen/X86/atomic_mi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic_mi.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/atomic_mi.ll (original)
+++ llvm/trunk/test/CodeGen/X86/atomic_mi.ll Wed Nov 14 13:11:53 2018
@@ -2245,11 +2245,11 @@ define void @fadd_array(i64* %arg, doubl
; X32-NEXT: .cfi_offset %edi, -16
; X32-NEXT: .cfi_offset %ebx, -12
; X32-NEXT: movl 20(%ebp), %esi
+; X32-NEXT: movl 8(%ebp), %edi
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: xorl %edx, %edx
; X32-NEXT: xorl %ecx, %ecx
; X32-NEXT: xorl %ebx, %ebx
-; X32-NEXT: movl 8(%ebp), %edi
; X32-NEXT: lock cmpxchg8b (%edi,%esi,8)
; X32-NEXT: movl %edx, {{[0-9]+}}(%esp)
; X32-NEXT: movl %eax, {{[0-9]+}}(%esp)
Modified: llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx512-regcall-NoMask.ll Wed Nov 14 13:11:53 2018
@@ -1252,17 +1252,17 @@ define x86_regcallcc %struct.complex @te
; WIN64-LABEL: test_argMultiRet:
; WIN64: # %bb.0:
; WIN64-NEXT: vaddsd __real@{{.*}}(%rip), %xmm1, %xmm1
+; WIN64-NEXT: movl $999, %edx # imm = 0x3E7
; WIN64-NEXT: movl $4, %eax
; WIN64-NEXT: movb $7, %cl
-; WIN64-NEXT: movl $999, %edx # imm = 0x3E7
; WIN64-NEXT: retq
;
; LINUXOSX64-LABEL: test_argMultiRet:
; LINUXOSX64: # %bb.0:
; LINUXOSX64-NEXT: vaddsd {{.*}}(%rip), %xmm1, %xmm1
+; LINUXOSX64-NEXT: movl $999, %edx # imm = 0x3E7
; LINUXOSX64-NEXT: movl $4, %eax
; LINUXOSX64-NEXT: movb $7, %cl
-; LINUXOSX64-NEXT: movl $999, %edx # imm = 0x3E7
; LINUXOSX64-NEXT: retq
%6 = fadd double %1, 5.000000e+00
%7 = insertvalue %struct.complex undef, float %0, 0
Modified: llvm/trunk/test/CodeGen/X86/bss_pagealigned.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bss_pagealigned.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bss_pagealigned.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bss_pagealigned.ll Wed Nov 14 13:11:53 2018
@@ -7,9 +7,9 @@ declare i8* @memset(i8*, i32, i64)
define void @unxlate_dev_mem_ptr(i64 %phis, i8* %addr) nounwind {
%pte.addr.i = alloca %struct.kmem_cache_order_objects*
%call8 = call i8* @memset(i8* bitcast ([512 x %struct.kmem_cache_order_objects]* @bm_pte to i8*), i32 0, i64 4096)
-; CHECK: movq $bm_pte, %rdi
+; CHECK: movl $4096, %edx
+; CHECK-NEXT: movq $bm_pte, %rdi
; CHECK-NEXT: xorl %esi, %esi
-; CHECK-NEXT: movl $4096, %edx
; CHECK-NEXT: callq memset
ret void
}
Modified: llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bypass-slow-division-32.ll Wed Nov 14 13:11:53 2018
@@ -97,8 +97,8 @@ define i32 @Test_use_div_and_idiv(i32 %a
; CHECK-NEXT: testl $-256, %edi
; CHECK-NEXT: je .LBB3_4
; CHECK-NEXT: .LBB3_5:
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %ebx
; CHECK-NEXT: jmp .LBB3_6
; CHECK-NEXT: .LBB3_1:
Modified: llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bypass-slow-division-64.ll Wed Nov 14 13:11:53 2018
@@ -17,8 +17,8 @@ define i64 @Test_get_quotient(i64 %a, i6
; CHECK-NEXT: idivq %rsi
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB0_1:
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %esi
; CHECK-NEXT: # kill: def $eax killed $eax def $rax
; CHECK-NEXT: retq
@@ -40,8 +40,8 @@ define i64 @Test_get_remainder(i64 %a, i
; CHECK-NEXT: movq %rdx, %rax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB1_1:
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %esi
; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: retq
@@ -63,8 +63,8 @@ define i64 @Test_get_quotient_and_remain
; CHECK-NEXT: addq %rdx, %rax
; CHECK-NEXT: retq
; CHECK-NEXT: .LBB2_1:
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %esi
; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
; CHECK-NEXT: # kill: def $eax killed $eax def $rax
Modified: llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmpxchg-i128-i1.ll Wed Nov 14 13:11:53 2018
@@ -91,8 +91,8 @@ define i128 @cmpxchg_zext(i128* %addr, i
; CHECK-NEXT: movq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: sete %sil
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmpxchg16b.ll Wed Nov 14 13:11:53 2018
@@ -6,10 +6,10 @@ define void @t1(i128* nocapture %p) noun
; CHECK-LABEL: t1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx
+; CHECK-NEXT: movl $1, %ebx
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: movl $1, %ebx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/code-model-elf-memset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/code-model-elf-memset.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/code-model-elf-memset.ll (original)
+++ llvm/trunk/test/CodeGen/X86/code-model-elf-memset.ll Wed Nov 14 13:11:53 2018
@@ -30,8 +30,8 @@ define i32 @main() #0 {
; SMALL-PIC-NEXT: .cfi_def_cfa_offset 432
; SMALL-PIC-NEXT: movl $0, {{[0-9]+}}(%rsp)
; SMALL-PIC-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
-; SMALL-PIC-NEXT: xorl %esi, %esi
; SMALL-PIC-NEXT: movl $400, %edx # imm = 0x190
+; SMALL-PIC-NEXT: xorl %esi, %esi
; SMALL-PIC-NEXT: callq memset at PLT
; SMALL-PIC-NEXT: xorl %eax, %eax
; SMALL-PIC-NEXT: addq $424, %rsp # imm = 0x1A8
@@ -44,8 +44,8 @@ define i32 @main() #0 {
; MEDIUM-PIC-NEXT: .cfi_def_cfa_offset 432
; MEDIUM-PIC-NEXT: movl $0, {{[0-9]+}}(%rsp)
; MEDIUM-PIC-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
-; MEDIUM-PIC-NEXT: xorl %esi, %esi
; MEDIUM-PIC-NEXT: movl $400, %edx # imm = 0x190
+; MEDIUM-PIC-NEXT: xorl %esi, %esi
; MEDIUM-PIC-NEXT: callq memset at PLT
; MEDIUM-PIC-NEXT: xorl %eax, %eax
; MEDIUM-PIC-NEXT: addq $424, %rsp # imm = 0x1A8
@@ -57,14 +57,14 @@ define i32 @main() #0 {
; LARGE-PIC-NEXT: subq $424, %rsp # imm = 0x1A8
; LARGE-PIC-NEXT: .cfi_def_cfa_offset 432
; LARGE-PIC-NEXT: .L0$pb:
-; LARGE-PIC-NEXT: leaq .L0$pb(%rip), %rax
+; LARGE-PIC-NEXT: leaq .L0${{.*}}(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L0$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movl $0, {{[0-9]+}}(%rsp)
; LARGE-PIC-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
; LARGE-PIC-NEXT: movabsq $memset at GOT, %rax
-; LARGE-PIC-NEXT: xorl %esi, %esi
; LARGE-PIC-NEXT: movl $400, %edx # imm = 0x190
+; LARGE-PIC-NEXT: xorl %esi, %esi
; LARGE-PIC-NEXT: callq *(%rcx,%rax)
; LARGE-PIC-NEXT: xorl %eax, %eax
; LARGE-PIC-NEXT: addq $424, %rsp # imm = 0x1A8
Modified: llvm/trunk/test/CodeGen/X86/combine-srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srem.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srem.ll Wed Nov 14 13:11:53 2018
@@ -399,8 +399,8 @@ define i32 @ossfuzz6883() {
; CHECK-NEXT: cltd
; CHECK-NEXT: idivl %esi
; CHECK-NEXT: movl %edx, %edi
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divl %esi
; CHECK-NEXT: andl %edi, %eax
; CHECK-NEXT: retq
Modified: llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll Wed Nov 14 13:11:53 2018
@@ -7,9 +7,9 @@
; CHECK: callq _Z3fooPcjPKc
; CHECK: callq _Z3fooPcjPKc
; CHECK: movq %rsp, %rdi
-; CHECK: movl $4, %esi
; CHECK: testl {{%[a-z]+}}, {{%[a-z]+}}
; CHECK: je .LBB0_4
+; CHECK: movl $4, %esi
; Regenerate test with this command:
; clang++ -emit-llvm -S -O2 -g
Modified: llvm/trunk/test/CodeGen/X86/divrem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/divrem.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/divrem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/divrem.ll Wed Nov 14 13:11:53 2018
@@ -245,8 +245,8 @@ define void @ui16(i16 %x, i16 %y, i16* %
; X64: # %bb.0:
; X64-NEXT: movq %rdx, %r8
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: xorl %edx, %edx
; X64-NEXT: # kill: def $ax killed $ax killed $eax
+; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divw %si
; X64-NEXT: movw %ax, (%r8)
; X64-NEXT: movw %dx, (%rcx)
Modified: llvm/trunk/test/CodeGen/X86/known-bits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/known-bits.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/known-bits.ll (original)
+++ llvm/trunk/test/CodeGen/X86/known-bits.ll Wed Nov 14 13:11:53 2018
@@ -37,17 +37,17 @@ define void @knownbits_zext_in_reg(i8*)
; X32-NEXT: .LBB0_1: # %CF
; X32-NEXT: # =>This Loop Header: Depth=1
; X32-NEXT: # Child Loop BB0_2 Depth 2
-; X32-NEXT: xorl %edx, %edx
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X32-NEXT: divl {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X32-NEXT: xorl %edx, %edx
+; X32-NEXT: divl {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
-; X32-NEXT: divl (%esp) # 4-byte Folded Reload
; X32-NEXT: xorl %edx, %edx
+; X32-NEXT: divl (%esp) # 4-byte Folded Reload
; X32-NEXT: movl %edi, %eax
-; X32-NEXT: divl %esi
; X32-NEXT: xorl %edx, %edx
+; X32-NEXT: divl %esi
; X32-NEXT: movl %ebx, %eax
+; X32-NEXT: xorl %edx, %edx
; X32-NEXT: divl %ebp
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB0_2: # %CF237
@@ -87,17 +87,17 @@ define void @knownbits_zext_in_reg(i8*)
; X64-NEXT: .LBB0_1: # %CF
; X64-NEXT: # =>This Loop Header: Depth=1
; X64-NEXT: # Child Loop BB0_2 Depth 2
-; X64-NEXT: xorl %edx, %edx
; X64-NEXT: movl %r8d, %eax
-; X64-NEXT: divl %r9d
; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: divl %r9d
; X64-NEXT: movl %r10d, %eax
-; X64-NEXT: divl %r11d
; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: divl %r11d
; X64-NEXT: movl %edi, %eax
-; X64-NEXT: divl %ebx
; X64-NEXT: xorl %edx, %edx
+; X64-NEXT: divl %ebx
; X64-NEXT: movl %ecx, %eax
+; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divl %ebp
; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB0_2: # %CF237
Modified: llvm/trunk/test/CodeGen/X86/machine-cse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-cse.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/machine-cse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/machine-cse.ll Wed Nov 14 13:11:53 2018
@@ -63,8 +63,8 @@ define void @commute(i32 %test_case, i32
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: imull %edi, %esi
; CHECK-NEXT: leal (%rsi,%rsi,2), %esi
-; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: # kill: def $edi killed $edi killed $rdi
+; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq printf
; CHECK-NEXT: addq $8, %rsp
; CHECK-NEXT: .p2align 4, 0x90
Modified: llvm/trunk/test/CodeGen/X86/memset-nonzero.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memset-nonzero.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/memset-nonzero.ll (original)
+++ llvm/trunk/test/CodeGen/X86/memset-nonzero.ll Wed Nov 14 13:11:53 2018
@@ -144,8 +144,8 @@ define void @memset_256_nonzero_bytes(i8
; SSE: # %bb.0:
; SSE-NEXT: pushq %rax
; SSE-NEXT: .cfi_def_cfa_offset 16
-; SSE-NEXT: movl $42, %esi
; SSE-NEXT: movl $256, %edx # imm = 0x100
+; SSE-NEXT: movl $42, %esi
; SSE-NEXT: callq memset
; SSE-NEXT: popq %rax
; SSE-NEXT: .cfi_def_cfa_offset 8
Modified: llvm/trunk/test/CodeGen/X86/misched-code-difference-with-debug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched-code-difference-with-debug.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/misched-code-difference-with-debug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/misched-code-difference-with-debug.ll Wed Nov 14 13:11:53 2018
@@ -28,7 +28,7 @@ source_filename = "test/CodeGen/X86/misc
declare i32 @test_function(%class.C*, i8 signext, i8 signext, i8 signext, ...)
; CHECK-LABEL: test_without_debug
; CHECK: movl [[A:%[a-z]+]], [[B:%[a-z]+]]
-; CHECK-NEXT: movl [[A]], [[C:%[a-z]+]]
+; CHECK: movl [[A]], [[C:%[a-z]+]]
define void @test_without_debug() {
entry:
@@ -42,7 +42,7 @@ entry:
}
; CHECK-LABEL: test_with_debug
; CHECK: movl [[A]], [[B]]
-; CHECK-NEXT: movl [[A]], [[C]]
+; CHECK: movl [[A]], [[C]]
define void @test_with_debug() !dbg !17 {
entry:
Added: llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll?rev=346894&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll (added)
+++ llvm/trunk/test/CodeGen/X86/misched_phys_reg_assign_order.ll Wed Nov 14 13:11:53 2018
@@ -0,0 +1,52 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc %s -O2 -mtriple=i686-unknown-linux-gnu -o - | FileCheck %s
+
+ at f = global i8* zeroinitializer
+
+; PR39391 - The load of %v1 should be scheduled before the zeroing of the A-D registers.
+
+define void @g() #0 {
+; CHECK-LABEL: g:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: pushl %ebp
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: .cfi_offset %ebp, -8
+; CHECK-NEXT: movl %esp, %ebp
+; CHECK-NEXT: .cfi_def_cfa_register %ebp
+; CHECK-NEXT: pushl %ebx
+; CHECK-NEXT: pushl %esi
+; CHECK-NEXT: subl $16, %esp
+; CHECK-NEXT: .cfi_offset %esi, -16
+; CHECK-NEXT: .cfi_offset %ebx, -12
+; CHECK-NEXT: movl f, %esi
+; CHECK-NEXT: movb (%esi), %al
+; CHECK-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: xorl %ebx, %ebx
+; CHECK-NEXT: lock cmpxchg8b (%esi)
+; CHECK-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload
+; CHECK-NEXT: jne .LBB0_1
+; CHECK-NEXT: # %bb.2: # %k.end
+; CHECK-NEXT: .LBB0_1: # %.
+; CHECK-NEXT: calll m
+entry:
+ %p = load i8*, i8** @f
+ %v1 = load atomic i8, i8* %p monotonic, align 1
+ %d.h.h.h.h.h = bitcast i8* %p to i64*
+ %v2 = load atomic i64, i64* %d.h.h.h.h.h monotonic, align 8
+ %j.h = icmp eq i8 %v1, 0
+ br i1 %j.h, label %k.end, label %.
+
+.: ; preds = %entry
+ %v3 = call i32 @m()
+ unreachable
+
+k.end: ; preds = %entry
+ unreachable
+}
+
+declare i32 @m()
+
+attributes #0 = { "no-frame-pointer-elim-non-leaf" }
Modified: llvm/trunk/test/CodeGen/X86/patchpoint.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/patchpoint.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/patchpoint.ll (original)
+++ llvm/trunk/test/CodeGen/X86/patchpoint.ll Wed Nov 14 13:11:53 2018
@@ -103,8 +103,8 @@ define i64 @test_patchpoint_with_attribu
entry:
; CHECK-LABEL: test_patchpoint_with_attributes:
; CHECK: movl $42, %edi
-; CHECK: xorl %r10d, %r10d
; CHECK: movl $17, %esi
+; CHECK: xorl %r10d, %r10d
; CHECK: movabsq $_consume_attributes, %r11
; CHECK-NEXT: callq *%r11
; CHECK-NEXT: xchgw %ax, %ax
Modified: llvm/trunk/test/CodeGen/X86/pr32282.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr32282.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr32282.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr32282.ll Wed Nov 14 13:11:53 2018
@@ -52,8 +52,8 @@ define void @foo(i64 %x) nounwind {
; X64-NEXT: idivq %rcx
; X64-NEXT: jmp .LBB0_3
; X64-NEXT: .LBB0_1:
-; X64-NEXT: xorl %edx, %edx
; X64-NEXT: # kill: def $eax killed $eax killed $rax
+; X64-NEXT: xorl %edx, %edx
; X64-NEXT: divl %ecx
; X64-NEXT: # kill: def $eax killed $eax def $rax
; X64-NEXT: .LBB0_3:
Modified: llvm/trunk/test/CodeGen/X86/pr36865.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr36865.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr36865.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr36865.ll Wed Nov 14 13:11:53 2018
@@ -7,8 +7,8 @@ define void @main() {
; CHECK-NEXT: subq $424, %rsp # imm = 0x1A8
; CHECK-NEXT: .cfi_def_cfa_offset 432
; CHECK-NEXT: leaq {{[0-9]+}}(%rsp), %rdi
-; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: movl $400, %edx # imm = 0x190
+; CHECK-NEXT: xorl %esi, %esi
; CHECK-NEXT: callq memset
; CHECK-NEXT: movl {{[0-9]+}}(%rsp), %eax
; CHECK-NEXT: movl (%rax), %ecx
Modified: llvm/trunk/test/CodeGen/X86/pr38865.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr38865.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr38865.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr38865.ll Wed Nov 14 13:11:53 2018
@@ -15,11 +15,11 @@ define void @e() nounwind {
; CHECK-NEXT: subl $528, %esp # encoding: [0x81,0xec,0x10,0x02,0x00,0x00]
; CHECK-NEXT: # imm = 0x210
; CHECK-NEXT: leal {{[0-9]+}}(%rsp), %ebx # encoding: [0x8d,0x9c,0x24,0x08,0x01,0x00,0x00]
+; CHECK-NEXT: movl %ebx, %edi # encoding: [0x89,0xdf]
; CHECK-NEXT: movl $c, %esi # encoding: [0xbe,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 1, value: c, kind: FK_Data_4
; CHECK-NEXT: movl $260, %edx # encoding: [0xba,0x04,0x01,0x00,0x00]
; CHECK-NEXT: # imm = 0x104
-; CHECK-NEXT: movl %ebx, %edi # encoding: [0x89,0xdf]
; CHECK-NEXT: callq memcpy # encoding: [0xe8,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 1, value: memcpy-4, kind: FK_PCRel_4
; CHECK-NEXT: movl $32, %ecx # encoding: [0xb9,0x20,0x00,0x00,0x00]
Modified: llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll (original)
+++ llvm/trunk/test/CodeGen/X86/scalar_widen_div.ll Wed Nov 14 13:11:53 2018
@@ -237,12 +237,12 @@ define <3 x i64> @test_ulong_div(<3 x i6
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq %rcx
; CHECK-NEXT: movq %rax, %rcx
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq %r8
; CHECK-NEXT: movq %rax, %rsi
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movq %r10, %rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq %r9
; CHECK-NEXT: movq %rax, %rdi
; CHECK-NEXT: movq %rcx, %rax
@@ -372,22 +372,22 @@ define <5 x i64> @test_ulong_rem(<5 x i6
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rdx, %xmm0
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movq %rsi, %rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rdx, %xmm1
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movq %r8, %rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rdx, %xmm0
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movq %rcx, %rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rdx, %xmm2
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
-; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movq %r9, %rax
+; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: divq {{[0-9]+}}(%rsp)
; CHECK-NEXT: movq %rdx, 32(%rdi)
; CHECK-NEXT: movdqa %xmm2, 16(%rdi)
Modified: llvm/trunk/test/CodeGen/X86/shrink_vmul-widen.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink_vmul-widen.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shrink_vmul-widen.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shrink_vmul-widen.ll Wed Nov 14 13:11:53 2018
@@ -2373,23 +2373,23 @@ define void @PR34947(<9 x i16>* %p0, <9
; X86-AVX1-NEXT: divl %ecx
; X86-AVX1-NEXT: movl %edx, %ebp
; X86-AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: vpextrd $3, %xmm1, %ecx
+; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: divl %ecx
; X86-AVX1-NEXT: movl %edx, %ebx
-; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: vpextrd $2, %xmm0, %eax
; X86-AVX1-NEXT: vpextrd $2, %xmm1, %esi
+; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: divl %esi
; X86-AVX1-NEXT: movl %edx, %esi
-; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: vpextrd $1, %xmm0, %eax
; X86-AVX1-NEXT: vpextrd $1, %xmm1, %edi
+; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: divl %edi
; X86-AVX1-NEXT: movl %edx, %edi
-; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: vmovd %xmm0, %eax
; X86-AVX1-NEXT: vmovd %xmm1, %ecx
+; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: divl %ecx
; X86-AVX1-NEXT: vmovd %edx, %xmm0
; X86-AVX1-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
Modified: llvm/trunk/test/CodeGen/X86/shrink_vmul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink_vmul.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shrink_vmul.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shrink_vmul.ll Wed Nov 14 13:11:53 2018
@@ -2249,23 +2249,23 @@ define void @PR34947(<9 x i16>* %p0, <9
; X86-AVX1-NEXT: divl %ecx
; X86-AVX1-NEXT: movl %edx, %ebp
; X86-AVX1-NEXT: vpextrd $3, %xmm0, %eax
-; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: vpextrd $3, %xmm1, %ecx
+; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: divl %ecx
; X86-AVX1-NEXT: movl %edx, %ebx
-; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: vpextrd $2, %xmm0, %eax
; X86-AVX1-NEXT: vpextrd $2, %xmm1, %esi
+; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: divl %esi
; X86-AVX1-NEXT: movl %edx, %esi
-; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: vpextrd $1, %xmm0, %eax
; X86-AVX1-NEXT: vpextrd $1, %xmm1, %edi
+; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: divl %edi
; X86-AVX1-NEXT: movl %edx, %edi
-; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: vmovd %xmm0, %eax
; X86-AVX1-NEXT: vmovd %xmm1, %ecx
+; X86-AVX1-NEXT: xorl %edx, %edx
; X86-AVX1-NEXT: divl %ecx
; X86-AVX1-NEXT: vmovd %edx, %xmm0
; X86-AVX1-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
Modified: llvm/trunk/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll (original)
+++ llvm/trunk/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll Wed Nov 14 13:11:53 2018
@@ -62,7 +62,7 @@ define i32 @test_calls_and_rets(i32 *%pt
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr0(%rip), %rdx
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rdx
; X64-NOPIC-MCM-NEXT: cmpq %rdx, %rcx
; X64-NOPIC-MCM-NEXT: cmovneq %r14, %rax
; X64-NOPIC-MCM-NEXT: movl (%rbx), %ebp
@@ -73,7 +73,7 @@ define i32 @test_calls_and_rets(i32 *%pt
; X64-NOPIC-MCM-NEXT: movq %rsp, %rcx
; X64-NOPIC-MCM-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; X64-NOPIC-MCM-NEXT: sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr1(%rip), %rdx
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rdx
; X64-NOPIC-MCM-NEXT: cmpq %rdx, %rax
; X64-NOPIC-MCM-NEXT: cmovneq %r14, %rcx
; X64-NOPIC-MCM-NEXT: addl (%rbx), %ebp
@@ -102,7 +102,7 @@ define i32 @test_calls_and_rets(i32 *%pt
; X64-PIC-NEXT: movq %rsp, %rax
; X64-PIC-NEXT: movq -{{[0-9]+}}(%rsp), %rcx
; X64-PIC-NEXT: sarq $63, %rax
-; X64-PIC-NEXT: leaq .Lslh_ret_addr0(%rip), %rdx
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdx
; X64-PIC-NEXT: cmpq %rdx, %rcx
; X64-PIC-NEXT: cmovneq %r14, %rax
; X64-PIC-NEXT: movl (%rbx), %ebp
@@ -113,7 +113,7 @@ define i32 @test_calls_and_rets(i32 *%pt
; X64-PIC-NEXT: movq %rsp, %rcx
; X64-PIC-NEXT: movq -{{[0-9]+}}(%rsp), %rax
; X64-PIC-NEXT: sarq $63, %rcx
-; X64-PIC-NEXT: leaq .Lslh_ret_addr1(%rip), %rdx
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdx
; X64-PIC-NEXT: cmpq %rdx, %rax
; X64-PIC-NEXT: cmovneq %r14, %rcx
; X64-PIC-NEXT: addl (%rbx), %ebp
@@ -190,23 +190,23 @@ define i32 @test_calls_and_rets_noredzon
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr2(%rip), %rbp
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rbp
; X64-NOPIC-MCM-NEXT: callq f
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr2:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr2(%rip), %rcx
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rcx
; X64-NOPIC-MCM-NEXT: cmpq %rcx, %rbp
; X64-NOPIC-MCM-NEXT: cmovneq %r14, %rax
; X64-NOPIC-MCM-NEXT: movl (%rbx), %ebp
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr3(%rip), %r15
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %r15
; X64-NOPIC-MCM-NEXT: callq f
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr3:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rcx
; X64-NOPIC-MCM-NEXT: sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr3(%rip), %rax
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rax
; X64-NOPIC-MCM-NEXT: cmpq %rax, %r15
; X64-NOPIC-MCM-NEXT: cmovneq %r14, %rcx
; X64-NOPIC-MCM-NEXT: addl (%rbx), %ebp
@@ -234,23 +234,23 @@ define i32 @test_calls_and_rets_noredzon
; X64-PIC-NEXT: sarq $63, %rax
; X64-PIC-NEXT: shlq $47, %rax
; X64-PIC-NEXT: orq %rax, %rsp
-; X64-PIC-NEXT: leaq .Lslh_ret_addr2(%rip), %rbp
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rbp
; X64-PIC-NEXT: callq f at PLT
; X64-PIC-NEXT: .Lslh_ret_addr2:
; X64-PIC-NEXT: movq %rsp, %rax
; X64-PIC-NEXT: sarq $63, %rax
-; X64-PIC-NEXT: leaq .Lslh_ret_addr2(%rip), %rcx
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx
; X64-PIC-NEXT: cmpq %rcx, %rbp
; X64-PIC-NEXT: cmovneq %r14, %rax
; X64-PIC-NEXT: movl (%rbx), %ebp
; X64-PIC-NEXT: shlq $47, %rax
; X64-PIC-NEXT: orq %rax, %rsp
-; X64-PIC-NEXT: leaq .Lslh_ret_addr3(%rip), %r15
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %r15
; X64-PIC-NEXT: callq f at PLT
; X64-PIC-NEXT: .Lslh_ret_addr3:
; X64-PIC-NEXT: movq %rsp, %rcx
; X64-PIC-NEXT: sarq $63, %rcx
-; X64-PIC-NEXT: leaq .Lslh_ret_addr3(%rip), %rax
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rax
; X64-PIC-NEXT: cmpq %rax, %r15
; X64-PIC-NEXT: cmovneq %r14, %rcx
; X64-PIC-NEXT: addl (%rbx), %ebp
@@ -302,9 +302,9 @@ define i32 @test_call_setjmp(i32 *%ptr)
; X64-NOPIC-NEXT: cmpq $.Lslh_ret_addr4, %rbp
; X64-NOPIC-NEXT: cmovneq %r15, %rax
; X64-NOPIC-NEXT: movl (%rbx), %ebp
-; X64-NOPIC-NEXT: movl $42, %esi
; X64-NOPIC-NEXT: shlq $47, %rax
; X64-NOPIC-NEXT: movq %r14, %rdi
+; X64-NOPIC-NEXT: movl $42, %esi
; X64-NOPIC-NEXT: orq %rax, %rsp
; X64-NOPIC-NEXT: movq $.Lslh_ret_addr5, %r12
; X64-NOPIC-NEXT: callq sigsetjmp
@@ -314,10 +314,10 @@ define i32 @test_call_setjmp(i32 *%ptr)
; X64-NOPIC-NEXT: cmpq $.Lslh_ret_addr5, %r12
; X64-NOPIC-NEXT: cmovneq %r15, %rax
; X64-NOPIC-NEXT: addl (%rbx), %ebp
-; X64-NOPIC-NEXT: movl $42, %edx
; X64-NOPIC-NEXT: shlq $47, %rax
; X64-NOPIC-NEXT: movq %r14, %rdi
; X64-NOPIC-NEXT: movq %r14, %rsi
+; X64-NOPIC-NEXT: movl $42, %edx
; X64-NOPIC-NEXT: orq %rax, %rsp
; X64-NOPIC-NEXT: movq $.Lslh_ret_addr6, %r14
; X64-NOPIC-NEXT: callq __sigsetjmp
@@ -355,39 +355,39 @@ define i32 @test_call_setjmp(i32 *%ptr)
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: movq %r14, %rdi
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr4(%rip), %rbp
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rbp
; X64-NOPIC-MCM-NEXT: callq setjmp
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr4:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr4(%rip), %rcx
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rcx
; X64-NOPIC-MCM-NEXT: cmpq %rcx, %rbp
; X64-NOPIC-MCM-NEXT: cmovneq %r15, %rax
; X64-NOPIC-MCM-NEXT: movl (%rbx), %ebp
-; X64-NOPIC-MCM-NEXT: movl $42, %esi
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: movq %r14, %rdi
+; X64-NOPIC-MCM-NEXT: movl $42, %esi
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr5(%rip), %r12
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %r12
; X64-NOPIC-MCM-NEXT: callq sigsetjmp
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr5:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rax
; X64-NOPIC-MCM-NEXT: sarq $63, %rax
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr5(%rip), %rcx
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rcx
; X64-NOPIC-MCM-NEXT: cmpq %rcx, %r12
; X64-NOPIC-MCM-NEXT: cmovneq %r15, %rax
; X64-NOPIC-MCM-NEXT: addl (%rbx), %ebp
-; X64-NOPIC-MCM-NEXT: movl $42, %edx
; X64-NOPIC-MCM-NEXT: shlq $47, %rax
; X64-NOPIC-MCM-NEXT: movq %r14, %rdi
; X64-NOPIC-MCM-NEXT: movq %r14, %rsi
+; X64-NOPIC-MCM-NEXT: movl $42, %edx
; X64-NOPIC-MCM-NEXT: orq %rax, %rsp
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr6(%rip), %r14
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %r14
; X64-NOPIC-MCM-NEXT: callq __sigsetjmp
; X64-NOPIC-MCM-NEXT: .Lslh_ret_addr6:
; X64-NOPIC-MCM-NEXT: movq %rsp, %rcx
; X64-NOPIC-MCM-NEXT: sarq $63, %rcx
-; X64-NOPIC-MCM-NEXT: leaq .Lslh_ret_addr6(%rip), %rax
+; X64-NOPIC-MCM-NEXT: leaq {{.*}}(%rip), %rax
; X64-NOPIC-MCM-NEXT: cmpq %rax, %r14
; X64-NOPIC-MCM-NEXT: cmovneq %r15, %rcx
; X64-NOPIC-MCM-NEXT: addl (%rbx), %ebp
@@ -419,39 +419,39 @@ define i32 @test_call_setjmp(i32 *%ptr)
; X64-PIC-NEXT: shlq $47, %rax
; X64-PIC-NEXT: movq %r14, %rdi
; X64-PIC-NEXT: orq %rax, %rsp
-; X64-PIC-NEXT: leaq .Lslh_ret_addr4(%rip), %rbp
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rbp
; X64-PIC-NEXT: callq setjmp at PLT
; X64-PIC-NEXT: .Lslh_ret_addr4:
; X64-PIC-NEXT: movq %rsp, %rax
; X64-PIC-NEXT: sarq $63, %rax
-; X64-PIC-NEXT: leaq .Lslh_ret_addr4(%rip), %rcx
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx
; X64-PIC-NEXT: cmpq %rcx, %rbp
; X64-PIC-NEXT: cmovneq %r15, %rax
; X64-PIC-NEXT: movl (%rbx), %ebp
-; X64-PIC-NEXT: movl $42, %esi
; X64-PIC-NEXT: shlq $47, %rax
; X64-PIC-NEXT: movq %r14, %rdi
+; X64-PIC-NEXT: movl $42, %esi
; X64-PIC-NEXT: orq %rax, %rsp
-; X64-PIC-NEXT: leaq .Lslh_ret_addr5(%rip), %r12
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %r12
; X64-PIC-NEXT: callq sigsetjmp at PLT
; X64-PIC-NEXT: .Lslh_ret_addr5:
; X64-PIC-NEXT: movq %rsp, %rax
; X64-PIC-NEXT: sarq $63, %rax
-; X64-PIC-NEXT: leaq .Lslh_ret_addr5(%rip), %rcx
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx
; X64-PIC-NEXT: cmpq %rcx, %r12
; X64-PIC-NEXT: cmovneq %r15, %rax
; X64-PIC-NEXT: addl (%rbx), %ebp
-; X64-PIC-NEXT: movl $42, %edx
; X64-PIC-NEXT: shlq $47, %rax
; X64-PIC-NEXT: movq %r14, %rdi
; X64-PIC-NEXT: movq %r14, %rsi
+; X64-PIC-NEXT: movl $42, %edx
; X64-PIC-NEXT: orq %rax, %rsp
-; X64-PIC-NEXT: leaq .Lslh_ret_addr6(%rip), %r14
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %r14
; X64-PIC-NEXT: callq __sigsetjmp at PLT
; X64-PIC-NEXT: .Lslh_ret_addr6:
; X64-PIC-NEXT: movq %rsp, %rcx
; X64-PIC-NEXT: sarq $63, %rcx
-; X64-PIC-NEXT: leaq .Lslh_ret_addr6(%rip), %rax
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rax
; X64-PIC-NEXT: cmpq %rax, %r14
; X64-PIC-NEXT: cmovneq %r15, %rcx
; X64-PIC-NEXT: addl (%rbx), %ebp
Modified: llvm/trunk/test/CodeGen/X86/speculative-load-hardening-indirect.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/speculative-load-hardening-indirect.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/speculative-load-hardening-indirect.ll (original)
+++ llvm/trunk/test/CodeGen/X86/speculative-load-hardening-indirect.ll Wed Nov 14 13:11:53 2018
@@ -53,7 +53,7 @@ define i32 @test_indirect_call(i32 ()**
; X64-PIC-NEXT: movq %rsp, %rcx
; X64-PIC-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
; X64-PIC-NEXT: sarq $63, %rcx
-; X64-PIC-NEXT: leaq .Lslh_ret_addr0(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rbx, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -134,7 +134,7 @@ define i32 @test_indirect_call_global()
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq $-1, %rbx
; X64-NEXT: sarq $63, %rax
-; X64-NEXT: movq global_fnptr(%rip), %rcx
+; X64-NEXT: movq {{.*}}(%rip), %rcx
; X64-NEXT: orq %rax, %rcx
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
@@ -156,7 +156,7 @@ define i32 @test_indirect_call_global()
; X64-PIC-NEXT: movq %rsp, %rax
; X64-PIC-NEXT: movq $-1, %rbx
; X64-PIC-NEXT: sarq $63, %rax
-; X64-PIC-NEXT: movq global_fnptr at GOTPCREL(%rip), %rcx
+; X64-PIC-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx
; X64-PIC-NEXT: movq (%rcx), %rcx
; X64-PIC-NEXT: orq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rax
@@ -166,7 +166,7 @@ define i32 @test_indirect_call_global()
; X64-PIC-NEXT: movq %rsp, %rcx
; X64-PIC-NEXT: movq -{{[0-9]+}}(%rsp), %rdx
; X64-PIC-NEXT: sarq $63, %rcx
-; X64-PIC-NEXT: leaq .Lslh_ret_addr1(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rbx, %rcx
; X64-PIC-NEXT: shlq $47, %rcx
@@ -180,7 +180,7 @@ define i32 @test_indirect_call_global()
; X64-RETPOLINE-NEXT: movq %rsp, %rax
; X64-RETPOLINE-NEXT: movq $-1, %rbx
; X64-RETPOLINE-NEXT: sarq $63, %rax
-; X64-RETPOLINE-NEXT: movq global_fnptr(%rip), %r11
+; X64-RETPOLINE-NEXT: movq {{.*}}(%rip), %r11
; X64-RETPOLINE-NEXT: shlq $47, %rax
; X64-RETPOLINE-NEXT: orq %rax, %rsp
; X64-RETPOLINE-NEXT: callq __llvm_retpoline_r11
@@ -206,7 +206,7 @@ define i32 @test_indirect_tail_call_glob
; X64-NEXT: movq %rsp, %rax
; X64-NEXT: movq $-1, %rcx
; X64-NEXT: sarq $63, %rax
-; X64-NEXT: movq global_fnptr(%rip), %rcx
+; X64-NEXT: movq {{.*}}(%rip), %rcx
; X64-NEXT: orq %rax, %rcx
; X64-NEXT: shlq $47, %rax
; X64-NEXT: orq %rax, %rsp
@@ -217,7 +217,7 @@ define i32 @test_indirect_tail_call_glob
; X64-PIC-NEXT: movq %rsp, %rax
; X64-PIC-NEXT: movq $-1, %rcx
; X64-PIC-NEXT: sarq $63, %rax
-; X64-PIC-NEXT: movq global_fnptr at GOTPCREL(%rip), %rcx
+; X64-PIC-NEXT: movq global_fnptr@{{.*}}(%rip), %rcx
; X64-PIC-NEXT: movq (%rcx), %rcx
; X64-PIC-NEXT: orq %rax, %rcx
; X64-PIC-NEXT: shlq $47, %rax
@@ -229,7 +229,7 @@ define i32 @test_indirect_tail_call_glob
; X64-RETPOLINE-NEXT: movq %rsp, %rax
; X64-RETPOLINE-NEXT: movq $-1, %rcx
; X64-RETPOLINE-NEXT: sarq $63, %rax
-; X64-RETPOLINE-NEXT: movq global_fnptr(%rip), %r11
+; X64-RETPOLINE-NEXT: movq {{.*}}(%rip), %r11
; X64-RETPOLINE-NEXT: shlq $47, %rax
; X64-RETPOLINE-NEXT: orq %rax, %rsp
; X64-RETPOLINE-NEXT: jmp __llvm_retpoline_r11 # TAILCALL
@@ -251,24 +251,29 @@ define i32 @test_indirectbr(i8** %ptr) n
; X64-NEXT: .LBB4_1: # %bb0
; X64-NEXT: cmpq $.LBB4_1, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $2, %eax
-; X64-NEXT: jmp .LBB4_2
-; X64-NEXT: .LBB4_4: # %bb2
-; X64-NEXT: cmpq $.LBB4_4, %rdx
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
+; X64-NEXT: .LBB4_3: # %bb2
+; X64-NEXT: cmpq $.LBB4_3, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $13, %eax
-; X64-NEXT: jmp .LBB4_2
-; X64-NEXT: .LBB4_5: # %bb3
-; X64-NEXT: cmpq $.LBB4_5, %rdx
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
+; X64-NEXT: .LBB4_4: # %bb3
+; X64-NEXT: cmpq $.LBB4_4, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $42, %eax
-; X64-NEXT: jmp .LBB4_2
-; X64-NEXT: .LBB4_3: # %bb1
-; X64-NEXT: cmpq $.LBB4_3, %rdx
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
+; X64-NEXT: .LBB4_2: # %bb1
+; X64-NEXT: cmpq $.LBB4_2, %rdx
; X64-NEXT: cmovneq %rax, %rcx
-; X64-NEXT: movl $7, %eax
-; X64-NEXT: .LBB4_2: # %bb0
; X64-NEXT: shlq $47, %rcx
+; X64-NEXT: movl $7, %eax
; X64-NEXT: orq %rcx, %rsp
; X64-NEXT: retq
;
@@ -281,30 +286,35 @@ define i32 @test_indirectbr(i8** %ptr) n
; X64-PIC-NEXT: orq %rcx, %rdx
; X64-PIC-NEXT: jmpq *%rdx
; X64-PIC-NEXT: .LBB4_1: # %bb0
-; X64-PIC-NEXT: leaq .LBB4_1(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $2, %eax
-; X64-PIC-NEXT: jmp .LBB4_2
-; X64-PIC-NEXT: .LBB4_4: # %bb2
-; X64-PIC-NEXT: leaq .LBB4_4(%rip), %rsi
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
+; X64-PIC-NEXT: .LBB4_3: # %bb2
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $13, %eax
-; X64-PIC-NEXT: jmp .LBB4_2
-; X64-PIC-NEXT: .LBB4_5: # %bb3
-; X64-PIC-NEXT: leaq .LBB4_5(%rip), %rsi
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
+; X64-PIC-NEXT: .LBB4_4: # %bb3
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $42, %eax
-; X64-PIC-NEXT: jmp .LBB4_2
-; X64-PIC-NEXT: .LBB4_3: # %bb1
-; X64-PIC-NEXT: leaq .LBB4_3(%rip), %rsi
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
+; X64-PIC-NEXT: .LBB4_2: # %bb1
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
-; X64-PIC-NEXT: movl $7, %eax
-; X64-PIC-NEXT: .LBB4_2: # %bb0
; X64-PIC-NEXT: shlq $47, %rcx
+; X64-PIC-NEXT: movl $7, %eax
; X64-PIC-NEXT: orq %rcx, %rsp
; X64-PIC-NEXT: retq
;
@@ -341,27 +351,32 @@ define i32 @test_indirectbr_global(i32 %
; X64-NEXT: .LBB5_1: # %bb0
; X64-NEXT: cmpq $.LBB5_1, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $2, %eax
-; X64-NEXT: jmp .LBB5_2
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
; X64-NEXT: .Ltmp1: # Block address taken
-; X64-NEXT: .LBB5_4: # %bb2
-; X64-NEXT: cmpq $.LBB5_4, %rdx
+; X64-NEXT: .LBB5_3: # %bb2
+; X64-NEXT: cmpq $.LBB5_3, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $13, %eax
-; X64-NEXT: jmp .LBB5_2
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
; X64-NEXT: .Ltmp2: # Block address taken
-; X64-NEXT: .LBB5_5: # %bb3
-; X64-NEXT: cmpq $.LBB5_5, %rdx
+; X64-NEXT: .LBB5_4: # %bb3
+; X64-NEXT: cmpq $.LBB5_4, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $42, %eax
-; X64-NEXT: jmp .LBB5_2
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
; X64-NEXT: .Ltmp3: # Block address taken
-; X64-NEXT: .LBB5_3: # %bb1
-; X64-NEXT: cmpq $.LBB5_3, %rdx
+; X64-NEXT: .LBB5_2: # %bb1
+; X64-NEXT: cmpq $.LBB5_2, %rdx
; X64-NEXT: cmovneq %rax, %rcx
-; X64-NEXT: movl $7, %eax
-; X64-NEXT: .LBB5_2: # %bb0
; X64-NEXT: shlq $47, %rcx
+; X64-NEXT: movl $7, %eax
; X64-NEXT: orq %rcx, %rsp
; X64-NEXT: retq
;
@@ -371,39 +386,44 @@ define i32 @test_indirectbr_global(i32 %
; X64-PIC-NEXT: movq $-1, %rax
; X64-PIC-NEXT: sarq $63, %rcx
; X64-PIC-NEXT: movslq %edi, %rdx
-; X64-PIC-NEXT: movq global_blockaddrs at GOTPCREL(%rip), %rsi
+; X64-PIC-NEXT: movq global_blockaddrs@{{.*}}(%rip), %rsi
; X64-PIC-NEXT: movq (%rsi,%rdx,8), %rdx
; X64-PIC-NEXT: orq %rcx, %rdx
; X64-PIC-NEXT: jmpq *%rdx
; X64-PIC-NEXT: .Ltmp0: # Block address taken
; X64-PIC-NEXT: .LBB5_1: # %bb0
-; X64-PIC-NEXT: leaq .LBB5_1(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $2, %eax
-; X64-PIC-NEXT: jmp .LBB5_2
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .Ltmp1: # Block address taken
-; X64-PIC-NEXT: .LBB5_4: # %bb2
-; X64-PIC-NEXT: leaq .LBB5_4(%rip), %rsi
+; X64-PIC-NEXT: .LBB5_3: # %bb2
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $13, %eax
-; X64-PIC-NEXT: jmp .LBB5_2
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .Ltmp2: # Block address taken
-; X64-PIC-NEXT: .LBB5_5: # %bb3
-; X64-PIC-NEXT: leaq .LBB5_5(%rip), %rsi
+; X64-PIC-NEXT: .LBB5_4: # %bb3
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $42, %eax
-; X64-PIC-NEXT: jmp .LBB5_2
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .Ltmp3: # Block address taken
-; X64-PIC-NEXT: .LBB5_3: # %bb1
-; X64-PIC-NEXT: leaq .LBB5_3(%rip), %rsi
+; X64-PIC-NEXT: .LBB5_2: # %bb1
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
-; X64-PIC-NEXT: movl $7, %eax
-; X64-PIC-NEXT: .LBB5_2: # %bb0
; X64-PIC-NEXT: shlq $47, %rcx
+; X64-PIC-NEXT: movl $7, %eax
; X64-PIC-NEXT: orq %rcx, %rsp
; X64-PIC-NEXT: retq
;
@@ -416,36 +436,41 @@ define i32 @test_indirectbr_global(i32 %
; X64-RETPOLINE-NEXT: movq global_blockaddrs(,%rdx,8), %rdx
; X64-RETPOLINE-NEXT: orq %rcx, %rdx
; X64-RETPOLINE-NEXT: cmpq $2, %rdx
-; X64-RETPOLINE-NEXT: je .LBB6_5
+; X64-RETPOLINE-NEXT: je .LBB6_4
; X64-RETPOLINE-NEXT: # %bb.1: # %entry
; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx
; X64-RETPOLINE-NEXT: cmpq $3, %rdx
-; X64-RETPOLINE-NEXT: je .LBB6_6
+; X64-RETPOLINE-NEXT: je .LBB6_5
; X64-RETPOLINE-NEXT: # %bb.2: # %entry
; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx
; X64-RETPOLINE-NEXT: cmpq $4, %rdx
; X64-RETPOLINE-NEXT: jne .LBB6_3
; X64-RETPOLINE-NEXT: .Ltmp0: # Block address taken
-; X64-RETPOLINE-NEXT: # %bb.7: # %bb3
+; X64-RETPOLINE-NEXT: # %bb.6: # %bb3
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT: shlq $47, %rcx
; X64-RETPOLINE-NEXT: movl $42, %eax
-; X64-RETPOLINE-NEXT: jmp .LBB6_4
+; X64-RETPOLINE-NEXT: orq %rcx, %rsp
+; X64-RETPOLINE-NEXT: retq
; X64-RETPOLINE-NEXT: .Ltmp1: # Block address taken
-; X64-RETPOLINE-NEXT: .LBB6_5: # %bb1
+; X64-RETPOLINE-NEXT: .LBB6_4: # %bb1
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT: shlq $47, %rcx
; X64-RETPOLINE-NEXT: movl $7, %eax
-; X64-RETPOLINE-NEXT: jmp .LBB6_4
+; X64-RETPOLINE-NEXT: orq %rcx, %rsp
+; X64-RETPOLINE-NEXT: retq
; X64-RETPOLINE-NEXT: .Ltmp2: # Block address taken
-; X64-RETPOLINE-NEXT: .LBB6_6: # %bb2
+; X64-RETPOLINE-NEXT: .LBB6_5: # %bb2
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT: shlq $47, %rcx
; X64-RETPOLINE-NEXT: movl $13, %eax
-; X64-RETPOLINE-NEXT: jmp .LBB6_4
+; X64-RETPOLINE-NEXT: orq %rcx, %rsp
+; X64-RETPOLINE-NEXT: retq
; X64-RETPOLINE-NEXT: .Ltmp3: # Block address taken
; X64-RETPOLINE-NEXT: .LBB6_3: # %bb0
; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx
-; X64-RETPOLINE-NEXT: movl $2, %eax
-; X64-RETPOLINE-NEXT: .LBB6_4: # %bb0
; X64-RETPOLINE-NEXT: shlq $47, %rcx
+; X64-RETPOLINE-NEXT: movl $2, %eax
; X64-RETPOLINE-NEXT: orq %rcx, %rsp
; X64-RETPOLINE-NEXT: retq
entry:
@@ -482,31 +507,38 @@ define i32 @test_switch_jumptable(i32 %i
; X64-NEXT: movq .LJTI6_0(,%rdx,8), %rdx
; X64-NEXT: orq %rcx, %rdx
; X64-NEXT: jmpq *%rdx
-; X64-NEXT: .LBB6_4: # %bb1
-; X64-NEXT: cmpq $.LBB6_4, %rdx
+; X64-NEXT: .LBB6_3: # %bb1
+; X64-NEXT: cmpq $.LBB6_3, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $7, %eax
-; X64-NEXT: jmp .LBB6_3
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
; X64-NEXT: .LBB6_2: # %bb0
; X64-NEXT: cmovbeq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $2, %eax
-; X64-NEXT: jmp .LBB6_3
-; X64-NEXT: .LBB6_5: # %bb2
-; X64-NEXT: cmpq $.LBB6_5, %rdx
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
+; X64-NEXT: .LBB6_4: # %bb2
+; X64-NEXT: cmpq $.LBB6_4, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $13, %eax
-; X64-NEXT: jmp .LBB6_3
-; X64-NEXT: .LBB6_6: # %bb3
-; X64-NEXT: cmpq $.LBB6_6, %rdx
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
+; X64-NEXT: .LBB6_5: # %bb3
+; X64-NEXT: cmpq $.LBB6_5, %rdx
; X64-NEXT: cmovneq %rax, %rcx
+; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movl $42, %eax
-; X64-NEXT: jmp .LBB6_3
-; X64-NEXT: .LBB6_7: # %bb5
-; X64-NEXT: cmpq $.LBB6_7, %rdx
+; X64-NEXT: orq %rcx, %rsp
+; X64-NEXT: retq
+; X64-NEXT: .LBB6_6: # %bb5
+; X64-NEXT: cmpq $.LBB6_6, %rdx
; X64-NEXT: cmovneq %rax, %rcx
-; X64-NEXT: movl $11, %eax
-; X64-NEXT: .LBB6_3: # %bb0
; X64-NEXT: shlq $47, %rcx
+; X64-NEXT: movl $11, %eax
; X64-NEXT: orq %rcx, %rsp
; X64-NEXT: retq
;
@@ -520,40 +552,47 @@ define i32 @test_switch_jumptable(i32 %i
; X64-PIC-NEXT: # %bb.1: # %entry
; X64-PIC-NEXT: cmovaq %rax, %rcx
; X64-PIC-NEXT: movl %edi, %edx
-; X64-PIC-NEXT: leaq .LJTI6_0(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: movslq (%rsi,%rdx,4), %rdx
; X64-PIC-NEXT: addq %rsi, %rdx
; X64-PIC-NEXT: orq %rcx, %rdx
; X64-PIC-NEXT: jmpq *%rdx
-; X64-PIC-NEXT: .LBB6_4: # %bb1
-; X64-PIC-NEXT: leaq .LBB6_4(%rip), %rsi
+; X64-PIC-NEXT: .LBB6_3: # %bb1
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $7, %eax
-; X64-PIC-NEXT: jmp .LBB6_3
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
; X64-PIC-NEXT: .LBB6_2: # %bb0
; X64-PIC-NEXT: cmovbeq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $2, %eax
-; X64-PIC-NEXT: jmp .LBB6_3
-; X64-PIC-NEXT: .LBB6_5: # %bb2
-; X64-PIC-NEXT: leaq .LBB6_5(%rip), %rsi
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
+; X64-PIC-NEXT: .LBB6_4: # %bb2
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $13, %eax
-; X64-PIC-NEXT: jmp .LBB6_3
-; X64-PIC-NEXT: .LBB6_6: # %bb3
-; X64-PIC-NEXT: leaq .LBB6_6(%rip), %rsi
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
+; X64-PIC-NEXT: .LBB6_5: # %bb3
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
+; X64-PIC-NEXT: shlq $47, %rcx
; X64-PIC-NEXT: movl $42, %eax
-; X64-PIC-NEXT: jmp .LBB6_3
-; X64-PIC-NEXT: .LBB6_7: # %bb5
-; X64-PIC-NEXT: leaq .LBB6_7(%rip), %rsi
+; X64-PIC-NEXT: orq %rcx, %rsp
+; X64-PIC-NEXT: retq
+; X64-PIC-NEXT: .LBB6_6: # %bb5
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: cmpq %rsi, %rdx
; X64-PIC-NEXT: cmovneq %rax, %rcx
-; X64-PIC-NEXT: movl $11, %eax
-; X64-PIC-NEXT: .LBB6_3: # %bb0
; X64-PIC-NEXT: shlq $47, %rcx
+; X64-PIC-NEXT: movl $11, %eax
; X64-PIC-NEXT: orq %rcx, %rsp
; X64-PIC-NEXT: retq
;
@@ -567,40 +606,47 @@ define i32 @test_switch_jumptable(i32 %i
; X64-RETPOLINE-NEXT: # %bb.1: # %entry
; X64-RETPOLINE-NEXT: cmovgq %rax, %rcx
; X64-RETPOLINE-NEXT: testl %edi, %edi
-; X64-RETPOLINE-NEXT: je .LBB7_8
+; X64-RETPOLINE-NEXT: je .LBB7_7
; X64-RETPOLINE-NEXT: # %bb.2: # %entry
; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx
; X64-RETPOLINE-NEXT: cmpl $1, %edi
; X64-RETPOLINE-NEXT: jne .LBB7_6
; X64-RETPOLINE-NEXT: # %bb.3: # %bb2
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT: shlq $47, %rcx
; X64-RETPOLINE-NEXT: movl $13, %eax
-; X64-RETPOLINE-NEXT: jmp .LBB7_7
+; X64-RETPOLINE-NEXT: orq %rcx, %rsp
+; X64-RETPOLINE-NEXT: retq
; X64-RETPOLINE-NEXT: .LBB7_4: # %entry
; X64-RETPOLINE-NEXT: cmovleq %rax, %rcx
; X64-RETPOLINE-NEXT: cmpl $2, %edi
-; X64-RETPOLINE-NEXT: je .LBB7_9
+; X64-RETPOLINE-NEXT: je .LBB7_8
; X64-RETPOLINE-NEXT: # %bb.5: # %entry
; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx
; X64-RETPOLINE-NEXT: cmpl $3, %edi
; X64-RETPOLINE-NEXT: jne .LBB7_6
-; X64-RETPOLINE-NEXT: # %bb.10: # %bb5
+; X64-RETPOLINE-NEXT: # %bb.9: # %bb5
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT: shlq $47, %rcx
; X64-RETPOLINE-NEXT: movl $11, %eax
-; X64-RETPOLINE-NEXT: jmp .LBB7_7
+; X64-RETPOLINE-NEXT: orq %rcx, %rsp
+; X64-RETPOLINE-NEXT: retq
; X64-RETPOLINE-NEXT: .LBB7_6:
; X64-RETPOLINE-NEXT: cmoveq %rax, %rcx
+; X64-RETPOLINE-NEXT: shlq $47, %rcx
; X64-RETPOLINE-NEXT: movl $2, %eax
-; X64-RETPOLINE-NEXT: jmp .LBB7_7
-; X64-RETPOLINE-NEXT: .LBB7_8: # %bb1
+; X64-RETPOLINE-NEXT: orq %rcx, %rsp
+; X64-RETPOLINE-NEXT: retq
+; X64-RETPOLINE-NEXT: .LBB7_7: # %bb1
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
+; X64-RETPOLINE-NEXT: shlq $47, %rcx
; X64-RETPOLINE-NEXT: movl $7, %eax
-; X64-RETPOLINE-NEXT: jmp .LBB7_7
-; X64-RETPOLINE-NEXT: .LBB7_9: # %bb3
+; X64-RETPOLINE-NEXT: orq %rcx, %rsp
+; X64-RETPOLINE-NEXT: retq
+; X64-RETPOLINE-NEXT: .LBB7_8: # %bb3
; X64-RETPOLINE-NEXT: cmovneq %rax, %rcx
-; X64-RETPOLINE-NEXT: movl $42, %eax
-; X64-RETPOLINE-NEXT: .LBB7_7: # %bb0
; X64-RETPOLINE-NEXT: shlq $47, %rcx
+; X64-RETPOLINE-NEXT: movl $42, %eax
; X64-RETPOLINE-NEXT: orq %rcx, %rsp
; X64-RETPOLINE-NEXT: retq
entry:
@@ -687,7 +733,7 @@ define i32 @test_switch_jumptable_fallth
; X64-PIC-NEXT: cmovaq %r10, %r9
; X64-PIC-NEXT: xorl %eax, %eax
; X64-PIC-NEXT: movl %edi, %esi
-; X64-PIC-NEXT: leaq .LJTI7_0(%rip), %rdi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdi
; X64-PIC-NEXT: movslq (%rdi,%rsi,4), %rsi
; X64-PIC-NEXT: addq %rdi, %rsi
; X64-PIC-NEXT: orq %r9, %rsi
@@ -696,30 +742,30 @@ define i32 @test_switch_jumptable_fallth
; X64-PIC-NEXT: cmovbeq %r10, %r9
; X64-PIC-NEXT: movl (%rsi), %eax
; X64-PIC-NEXT: orl %r9d, %eax
-; X64-PIC-NEXT: leaq .LBB7_3(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: .LBB7_3: # %bb1
-; X64-PIC-NEXT: leaq .LBB7_3(%rip), %rdi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdi
; X64-PIC-NEXT: cmpq %rdi, %rsi
; X64-PIC-NEXT: cmovneq %r10, %r9
; X64-PIC-NEXT: addl (%rdx), %eax
; X64-PIC-NEXT: orl %r9d, %eax
-; X64-PIC-NEXT: leaq .LBB7_4(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: .LBB7_4: # %bb2
-; X64-PIC-NEXT: leaq .LBB7_4(%rip), %rdx
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rdx
; X64-PIC-NEXT: cmpq %rdx, %rsi
; X64-PIC-NEXT: cmovneq %r10, %r9
; X64-PIC-NEXT: addl (%rcx), %eax
; X64-PIC-NEXT: orl %r9d, %eax
-; X64-PIC-NEXT: leaq .LBB7_5(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: .LBB7_5: # %bb3
-; X64-PIC-NEXT: leaq .LBB7_5(%rip), %rcx
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx
; X64-PIC-NEXT: cmpq %rcx, %rsi
; X64-PIC-NEXT: cmovneq %r10, %r9
; X64-PIC-NEXT: addl (%r8), %eax
; X64-PIC-NEXT: orl %r9d, %eax
-; X64-PIC-NEXT: leaq .LBB7_6(%rip), %rsi
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rsi
; X64-PIC-NEXT: .LBB7_6: # %bb4
-; X64-PIC-NEXT: leaq .LBB7_6(%rip), %rcx
+; X64-PIC-NEXT: leaq {{.*}}(%rip), %rcx
; X64-PIC-NEXT: cmpq %rcx, %rsi
; X64-PIC-NEXT: cmovneq %r10, %r9
; X64-PIC-NEXT: shlq $47, %r9
Modified: llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll (original)
+++ llvm/trunk/test/CodeGen/X86/speculative-load-hardening.ll Wed Nov 14 13:11:53 2018
@@ -538,10 +538,10 @@ define void @test_basic_eh(i32 %a, i32*
; X64-NEXT: cmovneq %r15, %rcx
; X64-NEXT: movl %ebp, (%rax)
; X64-NEXT: .Ltmp0:
-; X64-NEXT: xorl %esi, %esi
-; X64-NEXT: xorl %edx, %edx
; X64-NEXT: shlq $47, %rcx
; X64-NEXT: movq %rax, %rdi
+; X64-NEXT: xorl %esi, %esi
+; X64-NEXT: xorl %edx, %edx
; X64-NEXT: orq %rcx, %rsp
; X64-NEXT: callq __cxa_throw
; X64-NEXT: .Lslh_ret_addr5:
@@ -612,9 +612,9 @@ define void @test_basic_eh(i32 %a, i32*
; X64-LFENCE-NEXT: callq __cxa_allocate_exception
; X64-LFENCE-NEXT: movl %ebp, (%rax)
; X64-LFENCE-NEXT: .Ltmp0:
+; X64-LFENCE-NEXT: movq %rax, %rdi
; X64-LFENCE-NEXT: xorl %esi, %esi
; X64-LFENCE-NEXT: xorl %edx, %edx
-; X64-LFENCE-NEXT: movq %rax, %rdi
; X64-LFENCE-NEXT: callq __cxa_throw
; X64-LFENCE-NEXT: .Ltmp1:
; X64-LFENCE-NEXT: .LBB4_2: # %exit
Modified: llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse42-intrinsics-x86.ll Wed Nov 14 13:11:53 2018
@@ -99,9 +99,9 @@ define i32 @test_x86_sse42_pcmpestria128
; X86-SSE-LABEL: test_x86_sse42_pcmpestria128:
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X86-SSE-NEXT: seta %bl ## encoding: [0x0f,0x97,0xc3]
; X86-SSE-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -111,9 +111,9 @@ define i32 @test_x86_sse42_pcmpestria128
; X86-AVX-LABEL: test_x86_sse42_pcmpestria128:
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X86-AVX-NEXT: seta %bl ## encoding: [0x0f,0x97,0xc3]
; X86-AVX-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -122,9 +122,9 @@ define i32 @test_x86_sse42_pcmpestria128
;
; X64-SSE-LABEL: test_x86_sse42_pcmpestria128:
; X64-SSE: ## %bb.0:
+; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X64-SSE-NEXT: seta %sil ## encoding: [0x40,0x0f,0x97,0xc6]
; X64-SSE-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -132,9 +132,9 @@ define i32 @test_x86_sse42_pcmpestria128
;
; X64-AVX-LABEL: test_x86_sse42_pcmpestria128:
; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X64-AVX-NEXT: seta %sil ## encoding: [0x40,0x0f,0x97,0xc6]
; X64-AVX-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -149,9 +149,9 @@ define i32 @test_x86_sse42_pcmpestric128
; X86-SSE-LABEL: test_x86_sse42_pcmpestric128:
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X86-SSE-NEXT: setb %bl ## encoding: [0x0f,0x92,0xc3]
; X86-SSE-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -161,9 +161,9 @@ define i32 @test_x86_sse42_pcmpestric128
; X86-AVX-LABEL: test_x86_sse42_pcmpestric128:
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X86-AVX-NEXT: setb %bl ## encoding: [0x0f,0x92,0xc3]
; X86-AVX-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -172,9 +172,9 @@ define i32 @test_x86_sse42_pcmpestric128
;
; X64-SSE-LABEL: test_x86_sse42_pcmpestric128:
; X64-SSE: ## %bb.0:
+; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X64-SSE-NEXT: setb %sil ## encoding: [0x40,0x0f,0x92,0xc6]
; X64-SSE-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -182,9 +182,9 @@ define i32 @test_x86_sse42_pcmpestric128
;
; X64-AVX-LABEL: test_x86_sse42_pcmpestric128:
; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X64-AVX-NEXT: setb %sil ## encoding: [0x40,0x0f,0x92,0xc6]
; X64-AVX-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -199,9 +199,9 @@ define i32 @test_x86_sse42_pcmpestrio128
; X86-SSE-LABEL: test_x86_sse42_pcmpestrio128:
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X86-SSE-NEXT: seto %bl ## encoding: [0x0f,0x90,0xc3]
; X86-SSE-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -211,9 +211,9 @@ define i32 @test_x86_sse42_pcmpestrio128
; X86-AVX-LABEL: test_x86_sse42_pcmpestrio128:
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X86-AVX-NEXT: seto %bl ## encoding: [0x0f,0x90,0xc3]
; X86-AVX-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -222,9 +222,9 @@ define i32 @test_x86_sse42_pcmpestrio128
;
; X64-SSE-LABEL: test_x86_sse42_pcmpestrio128:
; X64-SSE: ## %bb.0:
+; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X64-SSE-NEXT: seto %sil ## encoding: [0x40,0x0f,0x90,0xc6]
; X64-SSE-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -232,9 +232,9 @@ define i32 @test_x86_sse42_pcmpestrio128
;
; X64-AVX-LABEL: test_x86_sse42_pcmpestrio128:
; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X64-AVX-NEXT: seto %sil ## encoding: [0x40,0x0f,0x90,0xc6]
; X64-AVX-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -249,9 +249,9 @@ define i32 @test_x86_sse42_pcmpestris128
; X86-SSE-LABEL: test_x86_sse42_pcmpestris128:
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X86-SSE-NEXT: sets %bl ## encoding: [0x0f,0x98,0xc3]
; X86-SSE-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -261,9 +261,9 @@ define i32 @test_x86_sse42_pcmpestris128
; X86-AVX-LABEL: test_x86_sse42_pcmpestris128:
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X86-AVX-NEXT: sets %bl ## encoding: [0x0f,0x98,0xc3]
; X86-AVX-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -272,9 +272,9 @@ define i32 @test_x86_sse42_pcmpestris128
;
; X64-SSE-LABEL: test_x86_sse42_pcmpestris128:
; X64-SSE: ## %bb.0:
+; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X64-SSE-NEXT: sets %sil ## encoding: [0x40,0x0f,0x98,0xc6]
; X64-SSE-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -282,9 +282,9 @@ define i32 @test_x86_sse42_pcmpestris128
;
; X64-AVX-LABEL: test_x86_sse42_pcmpestris128:
; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X64-AVX-NEXT: sets %sil ## encoding: [0x40,0x0f,0x98,0xc6]
; X64-AVX-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -299,9 +299,9 @@ define i32 @test_x86_sse42_pcmpestriz128
; X86-SSE-LABEL: test_x86_sse42_pcmpestriz128:
; X86-SSE: ## %bb.0:
; X86-SSE-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-SSE-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X86-SSE-NEXT: sete %bl ## encoding: [0x0f,0x94,0xc3]
; X86-SSE-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -311,9 +311,9 @@ define i32 @test_x86_sse42_pcmpestriz128
; X86-AVX-LABEL: test_x86_sse42_pcmpestriz128:
; X86-AVX: ## %bb.0:
; X86-AVX-NEXT: pushl %ebx ## encoding: [0x53]
+; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X86-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X86-AVX-NEXT: xorl %ebx, %ebx ## encoding: [0x31,0xdb]
; X86-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X86-AVX-NEXT: sete %bl ## encoding: [0x0f,0x94,0xc3]
; X86-AVX-NEXT: movl %ebx, %eax ## encoding: [0x89,0xd8]
@@ -322,9 +322,9 @@ define i32 @test_x86_sse42_pcmpestriz128
;
; X64-SSE-LABEL: test_x86_sse42_pcmpestriz128:
; X64-SSE: ## %bb.0:
+; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-SSE-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-SSE-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-SSE-NEXT: pcmpestri $7, %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x3a,0x61,0xc1,0x07]
; X64-SSE-NEXT: sete %sil ## encoding: [0x40,0x0f,0x94,0xc6]
; X64-SSE-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
@@ -332,9 +332,9 @@ define i32 @test_x86_sse42_pcmpestriz128
;
; X64-AVX-LABEL: test_x86_sse42_pcmpestriz128:
; X64-AVX: ## %bb.0:
+; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: movl $7, %eax ## encoding: [0xb8,0x07,0x00,0x00,0x00]
; X64-AVX-NEXT: movl $7, %edx ## encoding: [0xba,0x07,0x00,0x00,0x00]
-; X64-AVX-NEXT: xorl %esi, %esi ## encoding: [0x31,0xf6]
; X64-AVX-NEXT: vpcmpestri $7, %xmm1, %xmm0 ## encoding: [0xc4,0xe3,0x79,0x61,0xc1,0x07]
; X64-AVX-NEXT: sete %sil ## encoding: [0x40,0x0f,0x94,0xc6]
; X64-AVX-NEXT: movl %esi, %eax ## encoding: [0x89,0xf0]
Modified: llvm/trunk/test/CodeGen/X86/vector-idiv-v2i32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-idiv-v2i32.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-idiv-v2i32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-idiv-v2i32.ll Wed Nov 14 13:11:53 2018
@@ -839,8 +839,8 @@ define void @test_udiv_v2i32(<2 x i32>*
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: divl %esi
; X86-NEXT: movl %eax, %esi
-; X86-NEXT: xorl %edx, %edx
; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: xorl %edx, %edx
; X86-NEXT: divl %ebx
; X86-NEXT: movd %eax, %xmm0
; X86-NEXT: movd %esi, %xmm1
@@ -885,8 +885,8 @@ define void @test_udiv_v2i32(<2 x i32>*
; X86_WIDEN-NEXT: xorl %edx, %edx
; X86_WIDEN-NEXT: divl (%ebx)
; X86_WIDEN-NEXT: movl %eax, %esi
-; X86_WIDEN-NEXT: xorl %edx, %edx
; X86_WIDEN-NEXT: movl %ecx, %eax
+; X86_WIDEN-NEXT: xorl %edx, %edx
; X86_WIDEN-NEXT: divl 4(%ebx)
; X86_WIDEN-NEXT: movl %eax, 4(%edi)
; X86_WIDEN-NEXT: movl %esi, (%edi)
@@ -943,8 +943,8 @@ define void @test_urem_v2i32(<2 x i32>*
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: divl %esi
; X86-NEXT: movl %edx, %esi
-; X86-NEXT: xorl %edx, %edx
; X86-NEXT: movl %ecx, %eax
+; X86-NEXT: xorl %edx, %edx
; X86-NEXT: divl %ebx
; X86-NEXT: movd %edx, %xmm0
; X86-NEXT: movd %esi, %xmm1
@@ -989,8 +989,8 @@ define void @test_urem_v2i32(<2 x i32>*
; X86_WIDEN-NEXT: xorl %edx, %edx
; X86_WIDEN-NEXT: divl (%ebx)
; X86_WIDEN-NEXT: movl %edx, %esi
-; X86_WIDEN-NEXT: xorl %edx, %edx
; X86_WIDEN-NEXT: movl %ecx, %eax
+; X86_WIDEN-NEXT: xorl %edx, %edx
; X86_WIDEN-NEXT: divl 4(%ebx)
; X86_WIDEN-NEXT: movl %edx, 4(%edi)
; X86_WIDEN-NEXT: movl %esi, (%edi)
Modified: llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x86-shrink-wrapping.ll Wed Nov 14 13:11:53 2018
@@ -427,41 +427,38 @@ if.end:
; Check that we handle calls to variadic functions correctly.
; CHECK-LABEL: callVariadicFunc:
;
+; ENABLE: movl %esi, %eax
; ENABLE: testl %edi, %edi
; ENABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
;
; Prologue code.
; CHECK: pushq
;
+; DISABLE: movl %esi, %eax
; DISABLE: testl %edi, %edi
; DISABLE-NEXT: je [[ELSE_LABEL:LBB[0-9_]+]]
;
; Setup of the varags.
-; CHECK: movl %esi, (%rsp)
-; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: %esi, %edi
-; CHECK-NEXT: %esi, %edx
-; CHECK-NEXT: %esi, %ecx
-; CHECK-NEXT: %esi, %r8d
-; CHECK-NEXT: %esi, %r9d
+; CHECK: movl %eax, (%rsp)
+; CHECK-NEXT: movl %eax, %edi
+; CHECK-NEXT: movl %eax, %esi
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: movl %eax, %r8d
+; CHECK-NEXT: movl %eax, %r9d
+; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: callq _someVariadicFunc
-; CHECK-NEXT: movl %eax, %esi
-; CHECK-NEXT: shll $3, %esi
+; CHECK-NEXT: shll $3, %eax
;
; ENABLE-NEXT: addq $8, %rsp
-; ENABLE-NEXT: movl %esi, %eax
; ENABLE-NEXT: retq
;
-; DISABLE: jmp [[IFEND_LABEL:LBB[0-9_]+]]
-;
+
; CHECK: [[ELSE_LABEL]]: ## %if.else
; Shift second argument by one and store into returned register.
-; CHECK: addl %esi, %esi
-;
-; DISABLE: [[IFEND_LABEL]]: ## %if.end
+; CHECK: addl %eax, %eax
;
; Epilogue code.
-; CHECK-NEXT: movl %esi, %eax
; DISABLE-NEXT: popq
; CHECK-NEXT: retq
define i32 @callVariadicFunc(i32 %cond, i32 %N) {
Modified: llvm/trunk/test/DebugInfo/X86/live-debug-values.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/live-debug-values.ll?rev=346894&r1=346893&r2=346894&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/live-debug-values.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/live-debug-values.ll Wed Nov 14 13:11:53 2018
@@ -33,7 +33,7 @@
; CHECK-NEXT: #DEBUG_VALUE: main:n <- $ebx
; Other register values have been clobbered.
; CHECK-NOT: #DEBUG_VALUE:
-; CHECK: movl %esi, m(%rip)
+; CHECK: movl %e{{..}}, m(%rip)
; ModuleID = 'LiveDebugValues.c'
source_filename = "test/DebugInfo/X86/live-debug-values.ll"
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