[PATCH] D54095: [X86] X86DAGToDAGISel::matchBitExtract(): extract 'lshr' from `X`
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 14 11:24:13 PST 2018
craig.topper added inline comments.
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Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:2874
+ if (ShiftAmt.getValueType() != MVT::i8) {
+ ShiftAmt = CurDAG->getNode(ISD::TRUNCATE, DL, MVT::i8, ShiftAmt);
+ insertDAGNode(*CurDAG, OrigShiftAmt, ShiftAmt);
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When does this ever happen? Type and op legalization should have canonicalized all shifts to use an i8 amount.
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Comment at: lib/Target/X86/X86ISelDAGToDAG.cpp:2879
+ // Now, *zero*-extend the shift amount. The bits 8...15 *must* be zero!
+ ShiftAmt = CurDAG->getNode(ISD::ZERO_EXTEND, DL, MVT::i16, ShiftAmt);
+ insertDAGNode(*CurDAG, OrigShiftAmt, ShiftAmt);
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Can we just directly zero extend to NVT and avoid the insert_subreg?
Repository:
rL LLVM
https://reviews.llvm.org/D54095
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