[llvm] r346704 - AMDGPU: Adding more median3 patterns
Aakanksha Patil via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 12 13:04:07 PST 2018
Author: aakanksha555
Date: Mon Nov 12 13:04:06 2018
New Revision: 346704
URL: http://llvm.org/viewvc/llvm-project?rev=346704&view=rev
Log:
AMDGPU: Adding more median3 patterns
min(max(a, b), max(min(a, b), c)) -> med3 a, b, c
Differential Revision: https://reviews.llvm.org/D54331
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
llvm/trunk/test/CodeGen/AMDGPU/smed3.ll
llvm/trunk/test/CodeGen/AMDGPU/umed3.ll
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td?rev=346704&r1=346703&r2=346704&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructions.td Mon Nov 12 13:04:06 2018
@@ -796,18 +796,30 @@ class ROTRPattern <Instruction BIT_ALIGN
(BIT_ALIGN $src0, $src0, $src1)
>;
-// This matches 16 permutations of
-// max(min(x, y), min(max(x, y), z))
-class IntMed3Pat<Instruction med3Inst,
+multiclass IntMed3Pat<Instruction med3Inst,
+ SDPatternOperator min,
SDPatternOperator max,
- SDPatternOperator max_oneuse,
SDPatternOperator min_oneuse,
- ValueType vt = i32> : AMDGPUPat<
+ SDPatternOperator max_oneuse,
+ ValueType vt = i32> {
+
+ // This matches 16 permutations of
+ // min(max(a, b), max(min(a, b), c))
+ def : AMDGPUPat <
+ (min (max_oneuse vt:$src0, vt:$src1),
+ (max_oneuse (min_oneuse vt:$src0, vt:$src1), vt:$src2)),
+ (med3Inst vt:$src0, vt:$src1, vt:$src2)
+>;
+
+ // This matches 16 permutations of
+ // max(min(x, y), min(max(x, y), z))
+ def : AMDGPUPat <
(max (min_oneuse vt:$src0, vt:$src1),
(min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)),
(med3Inst $src0, $src1, $src2)
>;
-
+}
+
// Special conversion patterns
def cvt_rpi_i32_f32 : PatFrag <
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=346704&r1=346703&r2=346704&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Mon Nov 12 13:04:06 2018
@@ -579,7 +579,8 @@ def : Pat <
(int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))),
(SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond))
>;
-// TODO: we could add more variants for other types of conditionals
+
+ // TODO: we could add more variants for other types of conditionals
//===----------------------------------------------------------------------===//
// VOP1 Patterns
@@ -1621,8 +1622,8 @@ defm : BFMPatterns <i32, S_BFM_B32, S_MO
defm : BFEPattern <V_BFE_U32, V_BFE_I32, S_MOV_B32>;
defm : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64, SReg_64>;
-def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>;
-def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>;
+defm : IntMed3Pat<V_MED3_I32, smin, smax, smin_oneuse, smax_oneuse>;
+defm : IntMed3Pat<V_MED3_U32, umin, umax, umin_oneuse, umax_oneuse>;
}
Modified: llvm/trunk/test/CodeGen/AMDGPU/smed3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/smed3.ll?rev=346704&r1=346703&r2=346704&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/smed3.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/smed3.ll Mon Nov 12 13:04:06 2018
@@ -364,6 +364,211 @@ bb:
ret void
}
+; 16 combinations
+
+; 16: min(max(x, y), max(min(x, y), z))
+; 17: min(max(x, y), max(min(y, x), z))
+; 18: min(max(x, y), max(z, min(x, y)))
+; 19: min(max(x, y), max(z, min(y, x)))
+; 20: min(max(y, x), max(min(x, y), z))
+; 21: min(max(y, x), max(min(y, x), z))
+; 22: min(max(y, x), max(z, min(x, y)))
+; 23: min(max(y, x), max(z, min(y, x)))
+;
+; + commute outermost min
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_16:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_16(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %x, i32 %y)
+ %tmp1 = call i32 @smax(i32 %x, i32 %y)
+ %tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_17:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_17(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %y, i32 %x)
+ %tmp1 = call i32 @smax(i32 %x, i32 %y)
+ %tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_18:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_18(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %x, i32 %y)
+ %tmp1 = call i32 @smax(i32 %x, i32 %y)
+ %tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_19:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_19(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %y, i32 %x)
+ %tmp1 = call i32 @smax(i32 %x, i32 %y)
+ %tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_20:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_20(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %x, i32 %y)
+ %tmp1 = call i32 @smax(i32 %y, i32 %x)
+ %tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_21:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_21(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %y, i32 %x)
+ %tmp1 = call i32 @smax(i32 %y, i32 %x)
+ %tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_22:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_22(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %x, i32 %y)
+ %tmp1 = call i32 @smax(i32 %y, i32 %x)
+ %tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_23:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_23(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %y, i32 %x)
+ %tmp1 = call i32 @smax(i32 %y, i32 %x)
+ %tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_24:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_24(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %x, i32 %y)
+ %tmp1 = call i32 @smax(i32 %x, i32 %y)
+ %tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_25:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_25(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %y, i32 %x)
+ %tmp1 = call i32 @smax(i32 %x, i32 %y)
+ %tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_26:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_26(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %x, i32 %y)
+ %tmp1 = call i32 @smax(i32 %x, i32 %y)
+ %tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_27:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_27(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %y, i32 %x)
+ %tmp1 = call i32 @smax(i32 %x, i32 %y)
+ %tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_28:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_28(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %x, i32 %y)
+ %tmp1 = call i32 @smax(i32 %y, i32 %x)
+ %tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_29:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_29(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %y, i32 %x)
+ %tmp1 = call i32 @smax(i32 %y, i32 %x)
+ %tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_30:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_30(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %x, i32 %y)
+ %tmp1 = call i32 @smax(i32 %y, i32 %x)
+ %tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_smed3_i32_pat_31:
+; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_smed3_i32_pat_31(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @smin(i32 %y, i32 %x)
+ %tmp1 = call i32 @smax(i32 %y, i32 %x)
+ %tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
; FIXME: Should keep scalar or not promote
; GCN-LABEL: {{^}}s_test_smed3_i16_pat_0:
; GCN: s_sext_i32_i16
Modified: llvm/trunk/test/CodeGen/AMDGPU/umed3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/umed3.ll?rev=346704&r1=346703&r2=346704&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/umed3.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/umed3.ll Mon Nov 12 13:04:06 2018
@@ -363,6 +363,212 @@ bb:
ret void
}
+; 16 combinations
+
+; 16: min(max(x, y), max(min(x, y), z))
+; 17: min(max(x, y), max(min(y, x), z))
+; 18: min(max(x, y), max(z, min(x, y)))
+; 19: min(max(x, y), max(z, min(y, x)))
+; 20: min(max(y, x), max(min(x, y), z))
+; 21: min(max(y, x), max(min(y, x), z))
+; 22: min(max(y, x), max(z, min(x, y)))
+; 23: min(max(y, x), max(z, min(y, x)))
+;
+; + commute outermost min
+
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_16:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_16(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %x, i32 %y)
+ %tmp1 = call i32 @umax(i32 %x, i32 %y)
+ %tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_17:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_17(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %y, i32 %x)
+ %tmp1 = call i32 @umax(i32 %x, i32 %y)
+ %tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_18:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_18(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %x, i32 %y)
+ %tmp1 = call i32 @umax(i32 %x, i32 %y)
+ %tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_19:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_19(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %y, i32 %x)
+ %tmp1 = call i32 @umax(i32 %x, i32 %y)
+ %tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_20:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_20(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %x, i32 %y)
+ %tmp1 = call i32 @umax(i32 %y, i32 %x)
+ %tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_21:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_21(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %y, i32 %x)
+ %tmp1 = call i32 @umax(i32 %y, i32 %x)
+ %tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_22:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_22(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %x, i32 %y)
+ %tmp1 = call i32 @umax(i32 %y, i32 %x)
+ %tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_23:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_23(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %y, i32 %x)
+ %tmp1 = call i32 @umax(i32 %y, i32 %x)
+ %tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_24:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_24(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %x, i32 %y)
+ %tmp1 = call i32 @umax(i32 %x, i32 %y)
+ %tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_25:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_25(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %y, i32 %x)
+ %tmp1 = call i32 @umax(i32 %x, i32 %y)
+ %tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_26:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_26(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %x, i32 %y)
+ %tmp1 = call i32 @umax(i32 %x, i32 %y)
+ %tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_27:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_27(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %y, i32 %x)
+ %tmp1 = call i32 @umax(i32 %x, i32 %y)
+ %tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_28:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_28(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %x, i32 %y)
+ %tmp1 = call i32 @umax(i32 %y, i32 %x)
+ %tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_29:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_29(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %y, i32 %x)
+ %tmp1 = call i32 @umax(i32 %y, i32 %x)
+ %tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
+ %tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_30:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_30(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %x, i32 %y)
+ %tmp1 = call i32 @umax(i32 %y, i32 %x)
+ %tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
+; GCN-LABEL: {{^}}s_test_umed3_i32_pat_31:
+; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+define amdgpu_kernel void @s_test_umed3_i32_pat_31(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
+bb:
+ %tmp0 = call i32 @umin(i32 %y, i32 %x)
+ %tmp1 = call i32 @umax(i32 %y, i32 %x)
+ %tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
+ %tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
+ store i32 %tmp3, i32 addrspace(1)* %arg
+ ret void
+}
+
; GCN-LABEL: {{^}}s_test_umed3_i16_pat_0:
; GCN: s_and_b32
; GCN: s_and_b32
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