[PATCH] D54392: [DAGCombiner] look through bitcasts when trying to narrow vector binops
Sanjay Patel via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 11 08:29:18 PST 2018
spatel created this revision.
spatel added reviewers: efriedma, craig.topper, RKSimon.
Herald added subscribers: kristof.beyls, javed.absar, mcrosier.
This is another step in vector narrowing - a follow-up to https://reviews.llvm.org/D53784 (and hoping to eventually squash potential regressions seen in https://reviews.llvm.org/D51553).
Most of the x86 test diffs are wins, but the AArch64 diff is probably not. Do we need the target hook to distinguish between "isExtractSubvectorCheap" and "isExtractSubvectorFree"?
This problem probably already exists independent of this patch, but it went unnoticed in the previous patch because there were no regression tests that showed that possibility.
The x86 diff in i64-mem-copy.ll is also close. Given the frequency throttling concerns with using wider vector ops, I think an extra extract to reduce vector width is a reasonable trade-off at this level of codegen, but if we're going to refine the target hook for AArch, we might adjust the x86 override too.
https://reviews.llvm.org/D54392
Files:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/AArch64/arm64-ld1.ll
test/CodeGen/X86/avx-vperm2x128.ll
test/CodeGen/X86/avx1-logical-load-folding.ll
test/CodeGen/X86/i64-mem-copy.ll
test/CodeGen/X86/pr36199.ll
test/CodeGen/X86/sad.ll
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