[PATCH] D54235: [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 9 10:01:41 PST 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL346528: [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx (authored by rampitec, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D54235?vs=173059&id=173370#toc
Repository:
rL LLVM
https://reviews.llvm.org/D54235
Files:
llvm/trunk/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
llvm/trunk/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
Index: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -229,11 +229,11 @@
}
bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const {
- return MI.findRegisterUseOperandIdx(R600::AR_X) != -1;
+ return MI.findRegisterUseOperandIdx(R600::AR_X, false, &RI) != -1;
}
bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const {
- return MI.findRegisterDefOperandIdx(R600::AR_X) != -1;
+ return MI.findRegisterDefOperandIdx(R600::AR_X, false, false, &RI) != -1;
}
bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const {
Index: llvm/trunk/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
+++ llvm/trunk/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp
@@ -226,11 +226,11 @@
// occur in the same basic block as its definition, because
// it is illegal for the scheduler to schedule them in
// different blocks.
- if (UseI->readsRegister(MOI->getReg()))
+ if (UseI->readsRegister(MOI->getReg(), &TRI))
LastUseCount = AluInstCount;
// Exit early if the current use kills the register
- if (UseI != Def && UseI->killsRegister(MOI->getReg()))
+ if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI))
break;
}
if (LastUseCount)
Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp
@@ -42,9 +42,12 @@
if (!FirstMI)
return true;
+ const MachineBasicBlock &MBB = *FirstMI->getParent();
+ const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
+ const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
const MachineOperand *Src2 = TII.getNamedOperand(SecondMI,
AMDGPU::OpName::src2);
- return FirstMI->definesRegister(Src2->getReg());
+ return FirstMI->definesRegister(Src2->getReg(), TRI);
}
default:
return false;
Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4934,10 +4934,10 @@
make_range(MachineBasicBlock::iterator(SCCDefInst),
SCCDefInst.getParent()->end())) {
// Exit if we find another SCC def.
- if (MI.findRegisterDefOperandIdx(AMDGPU::SCC) != -1)
+ if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1)
return;
- if (MI.findRegisterUseOperandIdx(AMDGPU::SCC) != -1)
+ if (MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI) != -1)
Worklist.insert(&MI);
}
}
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