[PATCH] D54276: [SelectionDAG][AArch64][X86] Move legalization of vector MULHS/MULHU from LegalizeDAG to LegalizeVectorOps

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, efriedma, zatrazz, SjoerdMeijer, fhahn, t.p.northover.
Herald added subscribers: kristof.beyls, javed.absar.

I believe we should be legalizing these with the rest of vector binary operations. If any custom lowering is required for these nodes, this will give the DAG combine between LegalizeVectorOps and LegalizeDAG to run on the custom code before constant build_vectors are lowered in LegalizeDAG.

Unfortunately, this regressed some AArch64 tests because that DAG combine is now combining (extract_subvector (build_vector)) into a narrower build_vector. This caused it to stop matching an isel pattern that was looking for a multipy and extract_subvector to generate u/smull2. Perhaps the MULHS/MULHU lowering should pick some new AArchISD node that can be directly matched u/smull2?

X86 is showing some weird code too due to aggressive constant broadcast formation using GPR even when it doesn't remove the BUILD_VECTOR completely.


https://reviews.llvm.org/D54276

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  test/CodeGen/AArch64/arm64-neon-mul-div-cte.ll
  test/CodeGen/AArch64/neon-idiv.ll
  test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
  test/CodeGen/AArch64/urem-seteq-vec-splat.ll
  test/CodeGen/X86/combine-udiv.ll
  test/CodeGen/X86/urem-seteq-vec-nonsplat.ll

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