[llvm] r346437 - [SelectionDAG] Assert on the width of DemandedElts argument to computeKnownBits for all vector typed operations not just build_vector.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu Nov  8 12:29:17 2018
New Revision: 346437

URL: http://llvm.org/viewvc/llvm-project?rev=346437&view=rev
Log:
[SelectionDAG] Assert on the width of DemandedElts argument to computeKnownBits for all vector typed operations not just build_vector.

Fix AArch64 unit test that fails with the assertion added.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/unittests/CodeGen/AArch64SelectionDAGTest.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=346437&r1=346436&r2=346437&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov  8 12:29:17 2018
@@ -2195,6 +2195,9 @@ KnownBits SelectionDAG::computeKnownBits
 
   KnownBits Known2;
   unsigned NumElts = DemandedElts.getBitWidth();
+  assert(!Op.getValueType().isVector() ||
+         NumElts == Op.getValueType().getVectorNumElements() &&
+         "Unexpected vector size");
 
   if (!DemandedElts)
     return Known;  // No demanded elts, better to assume we don't know anything.
@@ -2203,8 +2206,6 @@ KnownBits SelectionDAG::computeKnownBits
   switch (Opcode) {
   case ISD::BUILD_VECTOR:
     // Collect the known bits that are shared by every demanded vector element.
-    assert(NumElts == Op.getValueType().getVectorNumElements() &&
-           "Unexpected vector size");
     Known.Zero.setAllBits(); Known.One.setAllBits();
     for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
       if (!DemandedElts[i])

Modified: llvm/trunk/unittests/CodeGen/AArch64SelectionDAGTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CodeGen/AArch64SelectionDAGTest.cpp?rev=346437&r1=346436&r2=346437&view=diff
==============================================================================
--- llvm/trunk/unittests/CodeGen/AArch64SelectionDAGTest.cpp (original)
+++ llvm/trunk/unittests/CodeGen/AArch64SelectionDAGTest.cpp Thu Nov  8 12:29:17 2018
@@ -88,7 +88,7 @@ TEST_F(AArch64SelectionDAGTest, computeK
   auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2);
   auto InVec = DAG->getConstant(0, Loc, InVecVT);
   auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
-  auto DemandedElts = APInt(4, 15);
+  auto DemandedElts = APInt(2, 3);
   KnownBits Known;
   DAG->computeKnownBits(Op, Known, DemandedElts);
   EXPECT_TRUE(Known.isZero());
@@ -120,7 +120,7 @@ TEST_F(AArch64SelectionDAGTest, ComputeN
   auto OutVecVT = EVT::getVectorVT(Context, Int16VT, 2);
   auto InVec = DAG->getConstant(1, Loc, InVecVT);
   auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
-  auto DemandedElts = APInt(4, 15);
+  auto DemandedElts = APInt(2, 3);
   EXPECT_EQ(DAG->ComputeNumSignBits(Op, DemandedElts), 15u);
 }