[PATCH] D49531: [PowerPC] Enhance the selection(ISD::VSELECT) of vector type

Zixuan Wu via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 8 01:31:44 PST 2018


wuzish added a comment.

I think it's a workaround that use vsel instead of xxsel for v16i8 and v8i16. So maybe we can change back in another patch after fix the encountered failures in check-all to make the selection consistently.



================
Comment at: lib/Target/PowerPC/PPCInstrVSX.td:1159
+//def : Pat<(v8i16 (vselect v8i16:$vA, v8i16:$vB, v8i16:$vC)),
+//          (XXSEL $vC, $vB, $vA)>;
+def : Pat<(v4i32 (vselect v4i32:$vA, v4i32:$vB, v4i32:$vC)),
----------------
I can not use this pattern since the register class of XXSEL operand is vsrc, and it does not accept v16i8 or v8i16 as following registerclass definition.


```
def VRRC : RegisterClass<"PPC",
                         [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128],
                         128,
                         (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
                             V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
                             V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;

// VSX register classes (the allocation order mirrors that of the corresponding
// subregister classes).
def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
                          (add (sequence "VSL%u", 0, 13),
                               (sequence "VSL%u", 31, 14))>;
def VSRC  : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
                          (add VSLRC, VRRC)>;
```

if I add v16i8 and v8i16 into VSRC, it will cause many failures in check-all. But now v16i8 and v8i16 can not use xxsel but vsel although VSX is available. Why does VSRC RegisterClass not contain v16i8 and v8i16 like VRRC? Should I keep the patch and add v16i8 and v8i16 into VSRC and fix the failures in check-all?

@nemanjai @hfinkel 


================
Comment at: test/CodeGen/PowerPC/vsx.ll:485
 ; CHECK-REG: vcmpequh v4, v4, v5
-; CHECK-REG: xxsel v2, v3, v2, v4
+; CHECK-REG: vsel v2, v3, v2, v4
 ; CHECK-REG: blr
----------------
Since the reason I comment above, xxsel can not be selected.


https://reviews.llvm.org/D49531





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