[PATCH] D51524: [ARM64] [Windows] Handle funclets
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 7 14:51:23 PST 2018
efriedma added inline comments.
================
Comment at: lib/Target/AArch64/AArch64FrameLowering.cpp:2059
+ // emitPrologue if unwinding info is needed.
+ MF.setHasWinCFI(false);
+
----------------
thegameg wrote:
> Why is this needed?
It's not, as far as I can tell; I'll get rid of it.
================
Comment at: lib/Target/AArch64/AArch64RegisterInfo.cpp:260
+ // a base pointer if the stack is realigned.
+ if (MF.hasEHFunclets() && needsStackRealignment(MF))
+ return true;
----------------
thegameg wrote:
> Isn't this already caught by the next nested `if`s?
Yes, I refactored it and didn't realize it. Will fix.
================
Comment at: test/CodeGen/AArch64/wineh-try-catch-realign.ll:10
+; it shouldn't access the parent's frame via sp, and the prologue and
+; epilogue should be symmetrical.
+; CHECK-LABEL: "?catch$2@?0??a@@YAXXZ at 4HA":
----------------
thegameg wrote:
> Is there a chance that we can test the PEI/FrameLowering part with more specific MIR tests? Especially the checks for what the base register should be. The fact that we don't serialize `AArch64FunctionInfo` may make this impossible for now.
Yes, I could write an MIR test using -run-pass=prologepilog, but I don't see the point. The CHECK lines would be essentially identical, just checking for MIR opcodes instead of assembly instructions. The MIR doesn't directly record whether we have a base register, or what it is; it's only used as part of frame lowering.
Repository:
rL LLVM
https://reviews.llvm.org/D51524
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