[PATCH] D54225: AMDGPU/InsertWaitcnts: Some more const-correctness
Nicolai Hähnle via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 7 14:15:15 PST 2018
nhaehnle created this revision.
nhaehnle added reviewers: msearles, rampitec, scott.linder, kanarayan.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl, arsenm.
Repository:
rL LLVM
https://reviews.llvm.org/D54225
Files:
lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Index: lib/Target/AMDGPU/SIInsertWaitcnts.cpp
===================================================================
--- lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -178,14 +178,14 @@
}
}
- int32_t getScoreLB(InstCounterType T) {
+ int32_t getScoreLB(InstCounterType T) const {
assert(T < NUM_INST_CNTS);
if (T >= NUM_INST_CNTS)
return 0;
return ScoreLBs[T];
}
- int32_t getScoreUB(InstCounterType T) {
+ int32_t getScoreUB(InstCounterType T) const {
assert(T < NUM_INST_CNTS);
if (T >= NUM_INST_CNTS)
return 0;
@@ -268,7 +268,7 @@
return EventUBs[W];
}
- bool counterOutOfOrder(InstCounterType T);
+ bool counterOutOfOrder(InstCounterType T) const;
unsigned int updateByWait(InstCounterType T, int ScoreToWait);
void updateByEvent(const SIInstrInfo *TII, const SIRegisterInfo *TRI,
const MachineRegisterInfo *MRI, WaitEventType E,
@@ -755,7 +755,7 @@
// Where there are multiple types of event in the bracket of a counter,
// the decrement may go out of order.
-bool BlockWaitcntBrackets::counterOutOfOrder(InstCounterType T) {
+bool BlockWaitcntBrackets::counterOutOfOrder(InstCounterType T) const {
switch (T) {
case VM_CNT:
return false;
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