[PATCH] D54218: [MachineScheduler] Bias physical register immediate assignments
Nirav Dave via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 7 11:55:49 PST 2018
niravd created this revision.
niravd added reviewers: MatzeB, qcolombet, myatsina, pcc.
Herald added subscribers: jsji, jfb, arphaman, javed.absar, hiraditya, eraman, nhaehnle, jvesely, nemanjai.
The machine scheduler currently biases register copies to/from
physical registers to be closer to their point of use / def to
minimize their live ranges. This change extends this to also physical
register assignments from immediate values.
This causes a reduction in reduction in overall register pressure and
minor reduction in spills and indirectly fixes an out of register
assertion (PR39391).
Most test changes are from minor instruction reorderings and register
name selection changes and direct consequences of that.
Minor note:
CodeGen/X86/hoist-spill.ll now has an occurrence of chain spills as
in PR26810.
Repository:
rL LLVM
https://reviews.llvm.org/D54218
Files:
llvm/include/llvm/CodeGen/MachineScheduler.h
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86InstrInfo.td
llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
llvm/test/CodeGen/AArch64/extract-bits.ll
llvm/test/CodeGen/AArch64/funnel-shift.ll
llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
llvm/test/CodeGen/AArch64/sat-add.ll
llvm/test/CodeGen/AArch64/tail-call.ll
llvm/test/CodeGen/AArch64/urem-seteq-optsize.ll
llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll
llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll
llvm/test/CodeGen/AMDGPU/add.v2i16.ll
llvm/test/CodeGen/AMDGPU/addrspacecast.ll
llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
llvm/test/CodeGen/AMDGPU/bswap.ll
llvm/test/CodeGen/AMDGPU/call-argument-types.ll
llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
llvm/test/CodeGen/AMDGPU/calling-conventions.ll
llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
llvm/test/CodeGen/AMDGPU/ctpop64.ll
llvm/test/CodeGen/AMDGPU/ds_write2.ll
llvm/test/CodeGen/AMDGPU/ds_write2st64.ll
llvm/test/CodeGen/AMDGPU/fabs.f16.ll
llvm/test/CodeGen/AMDGPU/fcanonicalize.f16.ll
llvm/test/CodeGen/AMDGPU/fexp.ll
llvm/test/CodeGen/AMDGPU/fmax_legacy.f64.ll
llvm/test/CodeGen/AMDGPU/fmin_legacy.f64.ll
llvm/test/CodeGen/AMDGPU/fneg-combines.ll
llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
llvm/test/CodeGen/AMDGPU/fp-classify.ll
llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
llvm/test/CodeGen/AMDGPU/function-returns.ll
llvm/test/CodeGen/AMDGPU/global_smrd.ll
llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
llvm/test/CodeGen/AMDGPU/idot2.ll
llvm/test/CodeGen/AMDGPU/idot4.ll
llvm/test/CodeGen/AMDGPU/idot8.ll
llvm/test/CodeGen/AMDGPU/immv216.ll
llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
llvm/test/CodeGen/AMDGPU/infinite-loop.ll
llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll
llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
llvm/test/CodeGen/AMDGPU/kernel-args.ll
llvm/test/CodeGen/AMDGPU/known-never-snan.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.r600.read.local.size.ll
llvm/test/CodeGen/AMDGPU/llvm.round.ll
llvm/test/CodeGen/AMDGPU/local-atomics64.ll
llvm/test/CodeGen/AMDGPU/macro-fusion-cluster-vcc-uses.mir
llvm/test/CodeGen/AMDGPU/madak.ll
llvm/test/CodeGen/AMDGPU/merge-store-crash.ll
llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll
llvm/test/CodeGen/AMDGPU/mul.ll
llvm/test/CodeGen/AMDGPU/mul_int24.ll
llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
llvm/test/CodeGen/AMDGPU/or.ll
llvm/test/CodeGen/AMDGPU/permute.ll
llvm/test/CodeGen/AMDGPU/ret.ll
llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.ll
llvm/test/CodeGen/AMDGPU/select-i1.ll
llvm/test/CodeGen/AMDGPU/select.f16.ll
llvm/test/CodeGen/AMDGPU/setcc-opt.ll
llvm/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll
llvm/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
llvm/test/CodeGen/AMDGPU/shift-i128.ll
llvm/test/CodeGen/AMDGPU/shl.v2i16.ll
llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll
llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
llvm/test/CodeGen/AMDGPU/sign_extend.ll
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
llvm/test/CodeGen/AMDGPU/sub.i16.ll
llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
llvm/test/CodeGen/AMDGPU/trap.ll
llvm/test/CodeGen/AMDGPU/xor.ll
llvm/test/CodeGen/AMDGPU/zero_extend.ll
llvm/test/CodeGen/ARM/misched-fusion-lit.ll
llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll
llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
llvm/test/CodeGen/PowerPC/crbit-asm.ll
llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
llvm/test/CodeGen/PowerPC/i1-ext-fold.ll
llvm/test/CodeGen/PowerPC/indirectbr.ll
llvm/test/CodeGen/PowerPC/licm-remat.ll
llvm/test/CodeGen/PowerPC/pr33093.ll
llvm/test/CodeGen/PowerPC/pr35688.ll
llvm/test/CodeGen/PowerPC/setcc-logic.ll
llvm/test/CodeGen/PowerPC/signbit-shift.ll
llvm/test/CodeGen/PowerPC/subreg-postra-2.ll
llvm/test/CodeGen/PowerPC/testBitReverse.ll
llvm/test/CodeGen/SystemZ/DAGCombiner_isAlias.ll
llvm/test/CodeGen/SystemZ/pr36164.ll
llvm/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll
llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
llvm/test/CodeGen/X86/GlobalISel/ashr-scalar.ll
llvm/test/CodeGen/X86/GlobalISel/callingconv.ll
llvm/test/CodeGen/X86/GlobalISel/gep.ll
llvm/test/CodeGen/X86/GlobalISel/lshr-scalar.ll
llvm/test/CodeGen/X86/abi-isel.ll
llvm/test/CodeGen/X86/absolute-bt.ll
llvm/test/CodeGen/X86/add.ll
llvm/test/CodeGen/X86/anyext.ll
llvm/test/CodeGen/X86/atomic-eflags-reuse.ll
llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
llvm/test/CodeGen/X86/atomic_mi.ll
llvm/test/CodeGen/X86/avx-cmp.ll
llvm/test/CodeGen/X86/avx512-regcall-NoMask.ll
llvm/test/CodeGen/X86/bitreverse.ll
llvm/test/CodeGen/X86/bmi.ll
llvm/test/CodeGen/X86/bss_pagealigned.ll
llvm/test/CodeGen/X86/bug26810.ll
llvm/test/CodeGen/X86/bypass-slow-division-32.ll
llvm/test/CodeGen/X86/bypass-slow-division-64.ll
llvm/test/CodeGen/X86/cast-vsel.ll
llvm/test/CodeGen/X86/clear-highbits.ll
llvm/test/CodeGen/X86/clear-lowbits.ll
llvm/test/CodeGen/X86/clz.ll
llvm/test/CodeGen/X86/cmov.ll
llvm/test/CodeGen/X86/cmpxchg-i128-i1.ll
llvm/test/CodeGen/X86/cmpxchg16b.ll
llvm/test/CodeGen/X86/code-model-elf-memset.ll
llvm/test/CodeGen/X86/code-model-elf.ll
llvm/test/CodeGen/X86/combine-srem.ll
llvm/test/CodeGen/X86/critical-edge-split-2.ll
llvm/test/CodeGen/X86/dbg-changes-codegen-branch-folding.ll
llvm/test/CodeGen/X86/divrem.ll
llvm/test/CodeGen/X86/extract-bits.ll
llvm/test/CodeGen/X86/extract-lowbits.ll
llvm/test/CodeGen/X86/fast-isel-mem.ll
llvm/test/CodeGen/X86/funnel-shift.ll
llvm/test/CodeGen/X86/hoist-spill.ll
llvm/test/CodeGen/X86/instr-symbols.mir
llvm/test/CodeGen/X86/known-bits.ll
llvm/test/CodeGen/X86/lsr-static-addr.ll
llvm/test/CodeGen/X86/machine-cse.ll
llvm/test/CodeGen/X86/madd.ll
llvm/test/CodeGen/X86/masked_gather_scatter.ll
llvm/test/CodeGen/X86/memset-nonzero.ll
llvm/test/CodeGen/X86/misched-code-difference-with-debug.ll
llvm/test/CodeGen/X86/mul-constant-result.ll
llvm/test/CodeGen/X86/mul-i256.ll
llvm/test/CodeGen/X86/patchpoint.ll
llvm/test/CodeGen/X86/popcnt.ll
llvm/test/CodeGen/X86/pr29170.ll
llvm/test/CodeGen/X86/pr36865.ll
llvm/test/CodeGen/X86/pr38795.ll
llvm/test/CodeGen/X86/pr38865.ll
llvm/test/CodeGen/X86/pr39391.ll
llvm/test/CodeGen/X86/pr9517.ll
llvm/test/CodeGen/X86/required-vector-width.ll
llvm/test/CodeGen/X86/sad.ll
llvm/test/CodeGen/X86/sadd_sat.ll
llvm/test/CodeGen/X86/scalar_widen_div.ll
llvm/test/CodeGen/X86/scheduler-backtracking.ll
llvm/test/CodeGen/X86/select.ll
llvm/test/CodeGen/X86/select_const.ll
llvm/test/CodeGen/X86/shrink-compare.ll
llvm/test/CodeGen/X86/shrink_vmul.ll
llvm/test/CodeGen/X86/sink-hoist.ll
llvm/test/CodeGen/X86/speculative-load-hardening-call-and-ret.ll
llvm/test/CodeGen/X86/speculative-load-hardening-gather.ll
llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
llvm/test/CodeGen/X86/speculative-load-hardening.ll
llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll
llvm/test/CodeGen/X86/vec_fneg.ll
llvm/test/CodeGen/X86/vec_setcc-2.ll
llvm/test/CodeGen/X86/vector-idiv-v2i32.ll
llvm/test/CodeGen/X86/vector-rem.ll
llvm/test/CodeGen/X86/win32-eh.ll
llvm/test/CodeGen/X86/x86-cmov-converter.ll
llvm/test/CodeGen/X86/x86-shrink-wrapping.ll
llvm/test/CodeGen/X86/xmulo.ll
llvm/test/DebugInfo/X86/dbg-value-transfer-order.ll
llvm/test/DebugInfo/X86/inlined-indirect-value.ll
llvm/test/DebugInfo/X86/live-debug-values.ll
llvm/test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll
More information about the llvm-commits
mailing list