[PATCH] D54205: [RISCV] Add support for the various RISC-V FMA instruction variants

[Luís Marques via Phabricator via llvm-commits]

luismarques created this revision.
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Adds support for the various RISC-V FMA instructions (`fmadd`, `fmsub`, `fnmsub`, `fnmadd`).

The criteria for choosing whether a fused add or subtract is used, as well as whether the product is negated or not, is whether some of the arguments to the `llvm.fma.*` intrinsic are negated or not. In the tests, extraneous `fadd` instructions were added to avoid the negation being performed using a xor trick, which prevented the proper FMA forms from being selected and thus tested.

The FMA instruction patterns might seem incorrect (e.g., `fnmadd: -rs1 * rs2 - rs3`), but they should be correct. The misleading names were inherited from MIPS, where the negation happens after computing the sum.

The `llvm.fmuladd.*` intrinsics still do not generate RISC-V FMA instructions, as that depends on `TargetLowering::isFMAFasterthanFMulAndFAdd`.

Some comments in the test files about what type of instructions are there tested were updated, to better reflect the current content  of those test files.


Repository:
  rL LLVM

https://reviews.llvm.org/D54205

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfoD.td
  lib/Target/RISCV/RISCVInstrInfoF.td
  test/CodeGen/RISCV/alu32.ll
  test/CodeGen/RISCV/double-arith.ll
  test/CodeGen/RISCV/double-intrinsics.ll
  test/CodeGen/RISCV/float-arith.ll
  test/CodeGen/RISCV/float-intrinsics.ll

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