[PATCH] D54143: [WIP, RISCV] Generate address sequences suitable for mcmodel=medium

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 172915.
lewis-revill added a comment.

Deduplicate switch statements and error on an unsupported code model. Added a wrapper for loading the PC-relative address, which is expanded in `RISCVExpandPseudoInsts`. This approach is a compromise between splitting up into `auipc` and `addi` too early and blocking optimisations due to an additional basic block and splitting up too late and losing the chance to optimize the black box pseudo instruction.

By expanding at this point there is still the opportunity to do base-offset merges (when implemented) and other late machine-function passes, but the majority of larger optimisations such as outlining will have already taken place.

More changes are needed to fully implement this approach if it is suitable.


Repository:
  rL LLVM

https://reviews.llvm.org/D54143

Files:
  include/llvm/CodeGen/MachineBasicBlock.h
  lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVMCInstLower.cpp
  lib/Target/RISCV/Utils/RISCVBaseInfo.h
  test/CodeGen/RISCV/codemodel-lowering.ll

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