[llvm] r346253 - [AArch64][GlobalISel] Simplify and autogenerate the legalizer tests
Volkan Keles via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 6 10:59:18 PST 2018
Author: volkan
Date: Tue Nov 6 10:59:18 2018
New Revision: 346253
URL: http://llvm.org/viewvc/llvm-project?rev=346253&view=rev
Log:
[AArch64][GlobalISel] Simplify and autogenerate the legalizer tests
Modified:
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-add.mir Tue Nov 6 10:59:18 2018
@@ -1,37 +1,9 @@
-# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_scalar_add_big() {
- entry:
- ret void
- }
- define void @test_scalar_add_big_nonpow2() {
- entry:
- ret void
- }
- define void @test_scalar_add_small() {
- entry:
- ret void
- }
- define void @test_vector_add() {
- entry:
- ret void
- }
- define void @test_vector_add_nonpow2() {
- entry:
- ret void
- }
-...
-
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_scalar_add_big
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_scalar_add_big
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -47,63 +19,48 @@ body: |
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s64) = COPY $x3
- %4:_(s128) = G_MERGE_VALUES %0, %1
- %5:_(s128) = G_MERGE_VALUES %2, %3
+ %4:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
+ %5:_(s128) = G_MERGE_VALUES %2(s64), %3(s64)
%6:_(s128) = G_ADD %4, %5
- %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6
- $x0 = COPY %7
- $x1 = COPY %8
-...
+ %7:_(s64), %8:_(s64) = G_UNMERGE_VALUES %6(s128)
+ $x0 = COPY %7(s64)
+ $x1 = COPY %8(s64)
+...
---
name: test_scalar_add_big_nonpow2
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
- - { id: 9, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_scalar_add_big_nonpow2
- ; CHECK-NOT: G_MERGE_VALUES
- ; CHECK-NOT: G_UNMERGE_VALUES
- ; CHECK-DAG: [[CARRY0_32:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK-DAG: [[CARRY0:%[0-9]+]]:_(s1) = G_TRUNC [[CARRY0_32]]
- ; CHECK: [[RES_LO:%[0-9]+]]:_(s64), [[CARRY1:%[0-9]+]]:_(s1) = G_UADDE %0, %1, [[CARRY0]]
- ; CHECK: [[RES_MI:%[0-9]+]]:_(s64), [[CARRY2:%[0-9]+]]:_(s1) = G_UADDE %1, %2, [[CARRY1]]
- ; CHECK: [[RES_HI:%[0-9]+]]:_(s64), {{%.*}}(s1) = G_UADDE %2, %3, [[CARRY2]]
- ; CHECK-NOT: G_MERGE_VALUES
- ; CHECK-NOT: G_UNMERGE_VALUES
- ; CHECK: $x0 = COPY [[RES_LO]]
- ; CHECK: $x1 = COPY [[RES_MI]]
- ; CHECK: $x2 = COPY [[RES_HI]]
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[C]](s32)
+ ; CHECK: [[UADDE:%[0-9]+]]:_(s64), [[UADDE1:%[0-9]+]]:_(s1) = G_UADDE [[COPY]], [[COPY1]], [[TRUNC]]
+ ; CHECK: [[UADDE2:%[0-9]+]]:_(s64), [[UADDE3:%[0-9]+]]:_(s1) = G_UADDE [[COPY1]], [[COPY2]], [[UADDE1]]
+ ; CHECK: [[UADDE4:%[0-9]+]]:_(s64), [[UADDE5:%[0-9]+]]:_(s1) = G_UADDE [[COPY2]], [[COPY3]], [[UADDE3]]
+ ; CHECK: $x0 = COPY [[UADDE]](s64)
+ ; CHECK: $x1 = COPY [[UADDE2]](s64)
+ ; CHECK: $x2 = COPY [[UADDE4]](s64)
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s64) = COPY $x2
+ %3:_(s64) = COPY $x3
+ %4:_(s192) = G_MERGE_VALUES %0(s64), %1(s64), %2(s64)
+ %5:_(s192) = G_MERGE_VALUES %1(s64), %2(s64), %3(s64)
+ %6:_(s192) = G_ADD %4, %5
+ %7:_(s64), %8:_(s64), %9:_(s64) = G_UNMERGE_VALUES %6(s192)
+ $x0 = COPY %7(s64)
+ $x1 = COPY %8(s64)
+ $x2 = COPY %9(s64)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = COPY $x2
- %3(s64) = COPY $x3
- %4(s192) = G_MERGE_VALUES %0, %1, %2
- %5(s192) = G_MERGE_VALUES %1, %2, %3
- %6(s192) = G_ADD %4, %5
- %7(s64), %8(s64), %9(s64) = G_UNMERGE_VALUES %6
- $x0 = COPY %7
- $x1 = COPY %8
- $x2 = COPY %9
...
-
---
name: test_scalar_add_small
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_scalar_add_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -114,19 +71,17 @@ body: |
; CHECK: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
- %2:_(s8) = G_TRUNC %0
- %3:_(s8) = G_TRUNC %1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_ADD %2, %3
- %5:_(s64) = G_ANYEXT %4
- $x0 = COPY %5
-...
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x0 = COPY %5(s64)
+...
---
name: test_vector_add
-body: |
+body: |
bb.0.entry:
- liveins: $q0, $q1, $q2, $q3
-
; CHECK-LABEL: name: test_vector_add
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
@@ -140,50 +95,39 @@ body: |
%1:_(<2 x s64>) = COPY $q1
%2:_(<2 x s64>) = COPY $q2
%3:_(<2 x s64>) = COPY $q3
- %4:_(<4 x s64>) = G_MERGE_VALUES %0, %1
- %5:_(<4 x s64>) = G_MERGE_VALUES %2, %3
+ %4:_(<4 x s64>) = G_MERGE_VALUES %0(<2 x s64>), %1(<2 x s64>)
+ %5:_(<4 x s64>) = G_MERGE_VALUES %2(<2 x s64>), %3(<2 x s64>)
%6:_(<4 x s64>) = G_ADD %4, %5
- %7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6
- $q0 = COPY %7
- $q1 = COPY %8
+ %7:_(<2 x s64>), %8:_(<2 x s64>) = G_UNMERGE_VALUES %6(<4 x s64>)
+ $q0 = COPY %7(<2 x s64>)
+ $q1 = COPY %8(<2 x s64>)
+
...
---
name: test_vector_add_nonpow2
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
- - { id: 9, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $q0, $q1, $q2, $q3
; CHECK-LABEL: name: test_vector_add_nonpow2
- ; CHECK-NOT: G_EXTRACT
- ; CHECK-NOT: G_SEQUENCE
- ; CHECK: [[RES_LO:%[0-9]+]]:_(<2 x s64>) = G_ADD %0, %1
- ; CHECK: [[RES_MI:%[0-9]+]]:_(<2 x s64>) = G_ADD %1, %2
- ; CHECK: [[RES_HI:%[0-9]+]]:_(<2 x s64>) = G_ADD %2, %3
- ; CHECK-NOT: G_EXTRACT
- ; CHECK-NOT: G_SEQUENCE
- ; CHECK: $q0 = COPY [[RES_LO]]
- ; CHECK: $q1 = COPY [[RES_MI]]
- ; CHECK: $q2 = COPY [[RES_HI]]
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
+ ; CHECK: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK: [[ADD1:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY1]], [[COPY2]]
+ ; CHECK: [[ADD2:%[0-9]+]]:_(<2 x s64>) = G_ADD [[COPY2]], [[COPY3]]
+ ; CHECK: $q0 = COPY [[ADD]](<2 x s64>)
+ ; CHECK: $q1 = COPY [[ADD1]](<2 x s64>)
+ ; CHECK: $q2 = COPY [[ADD2]](<2 x s64>)
+ %0:_(<2 x s64>) = COPY $q0
+ %1:_(<2 x s64>) = COPY $q1
+ %2:_(<2 x s64>) = COPY $q2
+ %3:_(<2 x s64>) = COPY $q3
+ %4:_(<6 x s64>) = G_MERGE_VALUES %0(<2 x s64>), %1(<2 x s64>), %2(<2 x s64>)
+ %5:_(<6 x s64>) = G_MERGE_VALUES %1(<2 x s64>), %2(<2 x s64>), %3(<2 x s64>)
+ %6:_(<6 x s64>) = G_ADD %4, %5
+ %7:_(<2 x s64>), %8:_(<2 x s64>), %9:_(<2 x s64>) = G_UNMERGE_VALUES %6(<6 x s64>)
+ $q0 = COPY %7(<2 x s64>)
+ $q1 = COPY %8(<2 x s64>)
+ $q2 = COPY %9(<2 x s64>)
- %0(<2 x s64>) = COPY $q0
- %1(<2 x s64>) = COPY $q1
- %2(<2 x s64>) = COPY $q2
- %3(<2 x s64>) = COPY $q3
- %4(<6 x s64>) = G_MERGE_VALUES %0, %1, %2
- %5(<6 x s64>) = G_MERGE_VALUES %1, %2, %3
- %6(<6 x s64>) = G_ADD %4, %5
- %7(<2 x s64>), %8(<2 x s64>), %9(<2 x s64>) = G_UNMERGE_VALUES %6
- $q0 = COPY %7
- $q1 = COPY %8
- $q2 = COPY %9
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-and.mir Tue Nov 6 10:59:18 2018
@@ -1,29 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_scalar_and_small() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_scalar_and_small
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_scalar_and_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -34,13 +14,14 @@ body: |
; CHECK: $w0 = COPY [[COPY2]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: $x0 = COPY [[COPY3]](s64)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
- %4(s8) = G_AND %2, %3
- %6(s32) = G_ANYEXT %4
- $w0 = COPY %6
- %5(s64) = G_ANYEXT %2
- $x0 = COPY %5
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_AND %2, %3
+ %6:_(s32) = G_ANYEXT %4(s8)
+ $w0 = COPY %6(s32)
+ %5:_(s64) = G_ANYEXT %2(s8)
+ $x0 = COPY %5(s64)
+
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir Tue Nov 6 10:59:18 2018
@@ -1,36 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_icmp() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_icmp
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
- - { id: 9, class: _ }
- - { id: 10, class: _ }
- - { id: 11, class: _ }
- - { id: 12, class: _ }
- - { id: 13, class: _ }
- - { id: 14, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_icmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
@@ -50,22 +23,19 @@ body: |
; CHECK: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[INTTOPTR]](p0), [[INTTOPTR]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ICMP2]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x0
-
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
-
- %4(s1) = G_ICMP intpred(sge), %0, %1
- %11(s32) = G_ANYEXT %4
- $w0 = COPY %11
-
- %8(s1) = G_ICMP intpred(ult), %2, %3
- %12(s32) = G_ANYEXT %8
- $w0 = COPY %12
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x0
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s1) = G_ICMP intpred(sge), %0(s64), %1
+ %11:_(s32) = G_ANYEXT %4(s1)
+ $w0 = COPY %11(s32)
+ %8:_(s1) = G_ICMP intpred(ult), %2(s8), %3
+ %12:_(s32) = G_ANYEXT %8(s1)
+ $w0 = COPY %12(s32)
+ %9:_(p0) = G_INTTOPTR %0(s64)
+ %10:_(s1) = G_ICMP intpred(eq), %9(p0), %9
+ %14:_(s32) = G_ANYEXT %10(s1)
+ $w0 = COPY %14(s32)
- %9(p0) = G_INTTOPTR %0(s64)
- %10(s1) = G_ICMP intpred(eq), %9(p0), %9(p0)
- %14(s32) = G_ANYEXT %10
- $w0 = COPY %14
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-div.mir Tue Nov 6 10:59:18 2018
@@ -1,27 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_div() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_div
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_div
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -45,19 +27,15 @@ body: |
; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[AND]], [[AND1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UDIV]](s32)
; CHECK: $w0 = COPY [[COPY3]](s32)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
-
-
- %4(s8) = G_SDIV %2, %3
- %6:_(s32) = G_ANYEXT %4
- $w0 = COPY %6
-
-
- %5(s8) = G_UDIV %2, %3
- %7:_(s32) = G_ANYEXT %5
- $w0 = COPY %7
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_SDIV %2, %3
+ %6:_(s32) = G_ANYEXT %4(s8)
+ $w0 = COPY %6(s32)
+ %5:_(s8) = G_UDIV %2, %3
+ %7:_(s32) = G_ANYEXT %5(s8)
+ $w0 = COPY %7(s32)
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir Tue Nov 6 10:59:18 2018
@@ -1,40 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_ext() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_ext
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
- - { id: 9, class: _ }
- - { id: 10, class: _ }
- - { id: 11, class: _ }
- - { id: 12, class: _ }
- - { id: 13, class: _ }
- - { id: 14, class: _ }
- - { id: 15, class: _ }
- - { id: 16, class: _ }
- - { id: 17, class: _ }
- - { id: 18, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_ext
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
@@ -98,55 +67,48 @@ body: |
; CHECK: $w0 = COPY [[C8]](s32)
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK: $w0 = COPY [[DEF]](s32)
- %0(s64) = COPY $x0
-
- %1(s1) = G_TRUNC %0
- %19:_(s32) = G_ANYEXT %1
- $w0 = COPY %19
- %2(s8) = G_TRUNC %0
- %20:_(s32) = G_ANYEXT %2
- $w0 = COPY %20
- %3(s16) = G_TRUNC %0
- %21:_(s32) = G_ANYEXT %3
- $w0 = COPY %21
- %4(s32) = G_TRUNC %0
- $w0 = COPY %4
-
- %5(s64) = G_ANYEXT %1
- $x0 = COPY %5
- %6(s64) = G_ZEXT %2
- $x0 = COPY %6
- %7(s64) = G_ANYEXT %3
- $x0 = COPY %7
- %8(s64) = G_SEXT %4
- $x0 = COPY %8
-
- %9(s32) = G_SEXT %1
- $w0 = COPY %9
- %10(s32) = G_ZEXT %2
- $w0 = COPY %10
- %11(s32) = G_ANYEXT %3
- $w0 = COPY %11
-
- %12(s32) = G_ZEXT %1
- $w0 = COPY %12
- %13(s32) = G_ANYEXT %2
- $w0 = COPY %13
- %14(s32) = G_SEXT %3
- $w0 = COPY %14
-
- %15(s8) = G_ZEXT %1
- %22:_(s32) = G_ANYEXT %15
- $w0 = COPY %22
- %16(s16) = G_ANYEXT %2
- %23:_(s32) = G_ANYEXT %16
- $w0 = COPY %23
-
- %17(s32) = G_TRUNC %0
- $w0 = COPY %17
- %18(s64) = G_FPEXT %17
- $x0 = COPY %18
-
+ %0:_(s64) = COPY $x0
+ %1:_(s1) = G_TRUNC %0(s64)
+ %19:_(s32) = G_ANYEXT %1(s1)
+ $w0 = COPY %19(s32)
+ %2:_(s8) = G_TRUNC %0(s64)
+ %20:_(s32) = G_ANYEXT %2(s8)
+ $w0 = COPY %20(s32)
+ %3:_(s16) = G_TRUNC %0(s64)
+ %21:_(s32) = G_ANYEXT %3(s16)
+ $w0 = COPY %21(s32)
+ %4:_(s32) = G_TRUNC %0(s64)
+ $w0 = COPY %4(s32)
+ %5:_(s64) = G_ANYEXT %1(s1)
+ $x0 = COPY %5(s64)
+ %6:_(s64) = G_ZEXT %2(s8)
+ $x0 = COPY %6(s64)
+ %7:_(s64) = G_ANYEXT %3(s16)
+ $x0 = COPY %7(s64)
+ %8:_(s64) = G_SEXT %4(s32)
+ $x0 = COPY %8(s64)
+ %9:_(s32) = G_SEXT %1(s1)
+ $w0 = COPY %9(s32)
+ %10:_(s32) = G_ZEXT %2(s8)
+ $w0 = COPY %10(s32)
+ %11:_(s32) = G_ANYEXT %3(s16)
+ $w0 = COPY %11(s32)
+ %12:_(s32) = G_ZEXT %1(s1)
+ $w0 = COPY %12(s32)
+ %13:_(s32) = G_ANYEXT %2(s8)
+ $w0 = COPY %13(s32)
+ %14:_(s32) = G_SEXT %3(s16)
+ $w0 = COPY %14(s32)
+ %15:_(s8) = G_ZEXT %1(s1)
+ %22:_(s32) = G_ANYEXT %15(s8)
+ $w0 = COPY %22(s32)
+ %16:_(s16) = G_ANYEXT %2(s8)
+ %23:_(s32) = G_ANYEXT %16(s16)
+ $w0 = COPY %23(s32)
+ %17:_(s32) = G_TRUNC %0(s64)
+ $w0 = COPY %17(s32)
+ %18:_(s64) = G_FPEXT %17(s32)
+ $x0 = COPY %18(s64)
%24:_(s16) = G_IMPLICIT_DEF
%25:_(s32) = G_ZEXT %24(s16)
$w0 = COPY %25(s32)
@@ -154,4 +116,5 @@ body: |
$w0 = COPY %26(s32)
%27:_(s32) = G_ANYEXT %24(s16)
$w0 = COPY %27(s32)
+
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir Tue Nov 6 10:59:18 2018
@@ -1,24 +1,15 @@
-# RUN: llc -O0 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_extload(i8* %addr) {
- entry:
- ret void
- }
-...
-
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
---
name: test_extload
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_extload
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[LOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s32) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s32) = G_LOAD %0 :: (load 1)
$w0 = COPY %1
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir Tue Nov 6 10:59:18 2018
@@ -1,29 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_icmp() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_icmp
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_icmp
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
@@ -33,15 +13,13 @@ body: |
; CHECK: $w0 = COPY [[FCMP]](s32)
; CHECK: [[FCMP1:%[0-9]+]]:_(s32) = G_FCMP floatpred(uno), [[TRUNC]](s32), [[TRUNC1]]
; CHECK: $w0 = COPY [[FCMP1]](s32)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x0
-
- %2(s32) = G_TRUNC %0
- %3(s32) = G_TRUNC %1
-
- %4(s32) = G_FCMP floatpred(oge), %0, %1
- $w0 = COPY %4
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x0
+ %2:_(s32) = G_TRUNC %0(s64)
+ %3:_(s32) = G_TRUNC %1(s64)
+ %4:_(s32) = G_FCMP floatpred(oge), %0(s64), %1
+ $w0 = COPY %4(s32)
+ %5:_(s32) = G_FCMP floatpred(uno), %2(s32), %3
+ $w0 = COPY %5(s32)
- %5(s32) = G_FCMP floatpred(uno), %2, %3
- $w0 = COPY %5
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-gep.mir Tue Nov 6 10:59:18 2018
@@ -1,26 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_gep_small() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_gep_small
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_gep_small
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -30,9 +13,10 @@ body: |
; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SHL]], [[C]]
; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[ASHR]](s64)
; CHECK: $x0 = COPY [[GEP]](p0)
- %0(p0) = COPY $x0
- %1(s64) = COPY $x1
- %2(s8) = G_TRUNC %1
- %3(p0) = G_GEP %0, %2(s8)
- $x0 = COPY %3
+ %0:_(p0) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %1(s64)
+ %3:_(p0) = G_GEP %0, %2(s8)
+ $x0 = COPY %3(p0)
+
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir Tue Nov 6 10:59:18 2018
@@ -1,34 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_scalar_mul_small() {
- entry:
- ret void
- }
- define void @test_smul_overflow() {
- ret void
- }
- define void @test_umul_overflow() {
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_scalar_mul_small
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_scalar_mul_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -37,22 +12,19 @@ body: |
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[MUL]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
- %4(s8) = G_MUL %2, %3
- %5(s64) = G_ANYEXT %4
- $x0 = COPY %5
-...
-
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_MUL %2, %3
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x0 = COPY %5(s64)
+...
---
name: test_smul_overflow
-body: |
+body: |
bb.0:
- liveins: $x0, $x1, $w2, $w3
-
; CHECK-LABEL: name: test_smul_overflow
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -67,19 +39,15 @@ body: |
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64), %3:_(s1) = G_SMULO %0, %1
- $x0 = COPY %2
- %4:_(s32) = G_ANYEXT %3
- $w0 = COPY %4
+ $x0 = COPY %2(s64)
+ %4:_(s32) = G_ANYEXT %3(s1)
+ $w0 = COPY %4(s32)
...
-
-
---
name: test_umul_overflow
-body: |
+body: |
bb.0:
- liveins: $x0, $x1, $w2, $w3
-
; CHECK-LABEL: name: test_umul_overflow
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -93,8 +61,8 @@ body: |
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64), %3:_(s1) = G_UMULO %0, %1
- $x0 = COPY %2
- %4:_(s32) = G_ANYEXT %3
- $w0 = COPY %4
+ $x0 = COPY %2(s64)
+ %4:_(s32) = G_ANYEXT %3(s1)
+ $w0 = COPY %4(s32)
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-pow.mir Tue Nov 6 10:59:18 2018
@@ -1,40 +1,35 @@
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_pow() {
- entry:
- ret void
- }
-...
-
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_pow
-body: |
+body: |
bb.0.entry:
- liveins: $d0, $d1, $s2, $s3
-
; CHECK-LABEL: name: test_pow
- ; CHECK: hasCalls: true
-
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $d1
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $s2
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s3
+ ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: $d0 = COPY [[COPY]](s64)
+ ; CHECK: $d1 = COPY [[COPY1]](s64)
+ ; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $d0
+ ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: $x0 = COPY [[COPY4]](s64)
+ ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: $s0 = COPY [[COPY2]](s32)
+ ; CHECK: $s1 = COPY [[COPY3]](s32)
+ ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $s0
+ ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
+ ; CHECK: $w0 = COPY [[COPY5]](s32)
%0:_(s64) = COPY $d0
%1:_(s64) = COPY $d1
%2:_(s32) = COPY $s2
%3:_(s32) = COPY $s3
-
- ; CHECK: $d0 = COPY %0
- ; CHECK: $d1 = COPY %1
- ; CHECK: BL &pow, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $d0, implicit $d1, implicit-def $d0
- ; CHECK: %4:_(s64) = COPY $d0
%4:_(s64) = G_FPOW %0, %1
- $x0 = COPY %4
-
- ; CHECK: $s0 = COPY %2
- ; CHECK: $s1 = COPY %3
- ; CHECK: BL &powf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $s0, implicit $s1, implicit-def $s0
- ; CHECK: %5:_(s32) = COPY $s0
+ $x0 = COPY %4(s64)
%5:_(s32) = G_FPOW %2, %3
- $w0 = COPY %5
+ $w0 = COPY %5(s32)
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-rem.mir Tue Nov 6 10:59:18 2018
@@ -1,37 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_urem_64() {
- entry:
- ret void
- }
- define void @test_srem_32() {
- entry:
- ret void
- }
- define void @test_srem_8() {
- entry:
- ret void
- }
- define void @test_frem() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_urem_64
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_urem_64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -39,25 +11,16 @@ body: |
; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[UDIV]], [[COPY1]]
; CHECK: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[MUL]]
; CHECK: $x0 = COPY [[SUB]](s64)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_UREM %0, %1
- $x0 = COPY %2
-
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s64) = G_UREM %0, %1
+ $x0 = COPY %2(s64)
...
---
name: test_srem_32
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_srem_32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -67,27 +30,18 @@ body: |
; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[SDIV]], [[TRUNC1]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[MUL]]
; CHECK: $w0 = COPY [[SUB]](s32)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %3(s32) = G_TRUNC %0
- %4(s32) = G_TRUNC %1
- %5(s32) = G_SREM %3, %4
- $w0 = COPY %5
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s32) = G_TRUNC %0(s64)
+ %3:_(s32) = G_TRUNC %1(s64)
+ %4:_(s32) = G_SREM %2, %3
+ $w0 = COPY %4(s32)
...
---
name: test_srem_8
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
-
; CHECK-LABEL: name: test_srem_8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -108,27 +62,19 @@ body: |
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC3]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %6(s8) = G_TRUNC %0
- %7(s8) = G_TRUNC %1
- %8(s8) = G_SREM %6, %7
- %9:_(s32) = G_ANYEXT %8
- $w0 = COPY %9
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_SREM %2, %3
+ %5:_(s32) = G_ANYEXT %4(s8)
+ $w0 = COPY %5(s32)
+
...
---
name: test_frem
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_frem
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -148,12 +94,13 @@ body: |
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $s0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK: $w0 = COPY [[COPY3]](s32)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s64) = G_FREM %0, %1
- $x0 = COPY %2
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s64) = G_FREM %0, %1
+ $x0 = COPY %2(s64)
+ %3:_(s32) = G_TRUNC %0(s64)
+ %4:_(s32) = G_TRUNC %1(s64)
+ %5:_(s32) = G_FREM %3, %4
+ $w0 = COPY %5(s32)
- %3(s32) = G_TRUNC %0
- %4(s32) = G_TRUNC %1
- %5(s32) = G_FREM %3, %4
- $w0 = COPY %5
+...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sextload.mir Tue Nov 6 10:59:18 2018
@@ -1,24 +1,15 @@
-# RUN: llc -O0 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_zextload(i8* %addr) {
- entry:
- ret void
- }
-...
-
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
---
-name: test_zextload
+name: test_sextload
body: |
bb.0.entry:
liveins: $x0
- ; CHECK-LABEL: name: test_zextload
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK-LABEL: name: test_sextload
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s32) = G_SEXTLOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s32) = G_SEXTLOAD %0 :: (load 1)
$w0 = COPY %1
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir Tue Nov 6 10:59:18 2018
@@ -1,28 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_shift() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_shift
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
; CHECK-LABEL: name: test_shift
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -52,21 +33,18 @@ body: |
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[TRUNC4]], [[AND3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
; CHECK: $w0 = COPY [[COPY4]](s32)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
-
- %4(s8) = G_ASHR %2, %3
- %7:_(s32) = G_ANYEXT %4
- $w0 = COPY %7
-
-
- %5(s8) = G_LSHR %2, %3
- %8:_(s32) = G_ANYEXT %5
- $w0 = COPY %8
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_ASHR %2, %3
+ %7:_(s32) = G_ANYEXT %4(s8)
+ $w0 = COPY %7(s32)
+ %5:_(s8) = G_LSHR %2, %3
+ %8:_(s32) = G_ANYEXT %5(s8)
+ $w0 = COPY %8(s32)
+ %6:_(s8) = G_SHL %2, %3
+ %9:_(s32) = G_ANYEXT %6(s8)
+ $w0 = COPY %9(s32)
- %6(s8) = G_SHL %2, %3
- %9:_(s32) = G_ANYEXT %6
- $w0 = COPY %9
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir Tue Nov 6 10:59:18 2018
@@ -1,49 +1,10 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_simple() {
- entry:
- ret void
- next:
- ret void
- }
- define void @bitcast128() {
- ret void
- }
- define void @testExtOfCopyOfTrunc() {
- ret void
- }
- define void @testExtOf2CopyOfTrunc() {
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_simple
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
- - { id: 6, class: _ }
- - { id: 7, class: _ }
- - { id: 8, class: _ }
- - { id: 9, class: _ }
- - { id: 10, class: _ }
- - { id: 11, class: _ }
- - { id: 12, class: _ }
- - { id: 13, class: _ }
- - { id: 14, class: _ }
- - { id: 15, class: _ }
- - { id: 16, class: _ }
-body: |
+body: |
; CHECK-LABEL: name: test_simple
- ; CHECK: bb.0.{{[a-zA-Z0-9]+}}:
+ ; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s64)
@@ -52,7 +13,7 @@ body: |
; CHECK: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[INTTOPTR]](p0)
; CHECK: $x0 = COPY [[PTRTOINT]](s64)
; CHECK: G_BRCOND [[TRUNC]](s1), %bb.1
- ; CHECK: bb.1.{{[a-zA-Z0-9]+}}:
+ ; CHECK: bb.1:
; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[TRUNC]](s1), [[TRUNC2]], [[TRUNC3]]
@@ -83,127 +44,101 @@ body: |
; CHECK: [[BITCAST6:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST5]](<2 x s16>)
; CHECK: $w0 = COPY [[BITCAST6]](s32)
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
- %0(s64) = COPY $x0
+ successors: %bb.1(0x80000000)
- %1(s1) = G_TRUNC %0
- %2(s8) = G_TRUNC %0
- %3(s16) = G_TRUNC %0
- %4(s32) = G_TRUNC %0
-
- %5(p0) = G_INTTOPTR %0
- %6(s64) = G_PTRTOINT %5
- $x0 = COPY %6
-
- G_BRCOND %1, %bb.1
-
- bb.1.next:
-
- %7(s1) = G_SELECT %1, %1, %1
- %21:_(s32) = G_ANYEXT %7
- $w0 = COPY %21
-
- %8(s8) = G_SELECT %1, %2, %2
- %20:_(s32) = G_ANYEXT %8
- $w0 = COPY %20
-
- %9(s16) = G_SELECT %1, %3, %3
- %19:_(s32) = G_ANYEXT %9
- $w0 = COPY %19
-
- %10(s32) = G_SELECT %1, %4, %4
- %11(s64) = G_SELECT %1, %0, %0
- $x0 = COPY %11
-
- %12(<2 x s32>) = G_BITCAST %0
- %13(s64) = G_BITCAST %12
- $x0 = COPY %13
- %14(s32) = G_BITCAST %10
- $w0 = COPY %14
- %15(<4 x s8>) = G_BITCAST %0
- %17:_(s32) = G_BITCAST %15
- $w0 = COPY %17
- %16(<2 x s16>) = G_BITCAST %0
- %18:_(s32) = G_BITCAST %16
- $w0 = COPY %18
-...
+ %0:_(s64) = COPY $x0
+ %1:_(s1) = G_TRUNC %0(s64)
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s16) = G_TRUNC %0(s64)
+ %4:_(s32) = G_TRUNC %0(s64)
+ %5:_(p0) = G_INTTOPTR %0(s64)
+ %6:_(s64) = G_PTRTOINT %5(p0)
+ $x0 = COPY %6(s64)
+ G_BRCOND %1(s1), %bb.1
+
+ bb.1:
+ %7:_(s1) = G_SELECT %1(s1), %1, %1
+ %17:_(s32) = G_ANYEXT %7(s1)
+ $w0 = COPY %17(s32)
+ %8:_(s8) = G_SELECT %1(s1), %2, %2
+ %18:_(s32) = G_ANYEXT %8(s8)
+ $w0 = COPY %18(s32)
+ %9:_(s16) = G_SELECT %1(s1), %3, %3
+ %19:_(s32) = G_ANYEXT %9(s16)
+ $w0 = COPY %19(s32)
+ %10:_(s32) = G_SELECT %1(s1), %4, %4
+ %11:_(s64) = G_SELECT %1(s1), %0, %0
+ $x0 = COPY %11(s64)
+ %12:_(<2 x s32>) = G_BITCAST %0(s64)
+ %13:_(s64) = G_BITCAST %12(<2 x s32>)
+ $x0 = COPY %13(s64)
+ %14:_(s32) = G_BITCAST %10(s32)
+ $w0 = COPY %14(s32)
+ %15:_(<4 x s8>) = G_BITCAST %0(s64)
+ %20:_(s32) = G_BITCAST %15(<4 x s8>)
+ $w0 = COPY %20(s32)
+ %16:_(<2 x s16>) = G_BITCAST %0(s64)
+ %21:_(s32) = G_BITCAST %16(<2 x s16>)
+ $w0 = COPY %21(s32)
+...
---
name: bitcast128
-tracksRegLiveness: true
-registers:
- - { id: 0, class: _}
- - { id: 1, class: _}
- - { id: 2, class: _}
- - { id: 3, class: _}
body: |
- bb.1:
+ bb.0:
liveins: $x0, $x1
- ; This is legal and shouldn't be changed.
+
; CHECK-LABEL: name: bitcast128
- ; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[MV]](s128)
; CHECK: $q0 = COPY [[BITCAST]](<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %3(s128) = G_MERGE_VALUES %0(s64), %1(s64)
- %2(<2 x s64>) = G_BITCAST %3(s128)
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %3:_(s128) = G_MERGE_VALUES %0(s64), %1(s64)
+ %2:_(<2 x s64>) = G_BITCAST %3(s128)
$q0 = COPY %2(<2 x s64>)
RET_ReallyLR implicit $q0
...
---
name: testExtOfCopyOfTrunc
-tracksRegLiveness: true
-registers:
- - { id: 0, class: _}
- - { id: 1, class: _}
- - { id: 2, class: _}
- - { id: 3, class: _}
body: |
- bb.1:
+ bb.0:
liveins: $x0
+
; CHECK-LABEL: name: testExtOfCopyOfTrunc
- ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: $x0 = COPY [[COPY1]](s64)
; CHECK: RET_ReallyLR implicit $x0
- %0(s64) = COPY $x0
- %1(s1) = G_TRUNC %0
- %2(s1) = COPY %1
- %3(s64) = G_ANYEXT %2
- $x0 = COPY %3
+ %0:_(s64) = COPY $x0
+ %1:_(s1) = G_TRUNC %0(s64)
+ %2:_(s1) = COPY %1(s1)
+ %3:_(s64) = G_ANYEXT %2(s1)
+ $x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: testExtOf2CopyOfTrunc
-tracksRegLiveness: true
-registers:
- - { id: 0, class: _}
- - { id: 1, class: _}
- - { id: 2, class: _}
- - { id: 3, class: _}
body: |
- bb.1:
+ bb.0:
liveins: $x0
+
; CHECK-LABEL: name: testExtOf2CopyOfTrunc
- ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: $x0 = COPY [[COPY1]](s64)
; CHECK: RET_ReallyLR implicit $x0
- %0(s64) = COPY $x0
- %1(s1) = G_TRUNC %0
- %2(s1) = COPY %1
- %4:_(s1) = COPY %2
- %3(s64) = G_ANYEXT %4
- $x0 = COPY %3
+ %0:_(s64) = COPY $x0
+ %1:_(s1) = G_TRUNC %0(s64)
+ %2:_(s1) = COPY %1(s1)
+ %4:_(s1) = COPY %2(s1)
+ %3:_(s64) = G_ANYEXT %4(s1)
+ $x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir Tue Nov 6 10:59:18 2018
@@ -1,28 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_scalar_sub_small() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_scalar_sub_small
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_scalar_sub_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -31,11 +12,12 @@ body: |
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
- %4(s8) = G_SUB %2, %3
- %5(s64) = G_ANYEXT %4
- $x0 = COPY %5
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_SUB %2, %3
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x0 = COPY %5(s64)
+
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-undef.mir Tue Nov 6 10:59:18 2018
@@ -1,9 +1,7 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_implicit_def
-registers:
body: |
bb.0.entry:
liveins:
@@ -12,7 +10,9 @@ body: |
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[DEF]](s64), [[DEF1]](s64)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[MV]](s128)
+ ; CHECK: $x0 = COPY [[TRUNC]](s64)
%0:_(s128) = G_IMPLICIT_DEF
- %1:_(s64) = G_TRUNC %0
- $x0 = COPY %1
+ %1:_(s64) = G_TRUNC %0(s128)
+ $x0 = COPY %1(s64)
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-xor.mir Tue Nov 6 10:59:18 2018
@@ -1,28 +1,9 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_scalar_xor_small() {
- entry:
- ret void
- }
-...
-
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_scalar_xor_small
-registers:
- - { id: 0, class: _ }
- - { id: 1, class: _ }
- - { id: 2, class: _ }
- - { id: 3, class: _ }
- - { id: 4, class: _ }
- - { id: 5, class: _ }
-body: |
+body: |
bb.0.entry:
- liveins: $x0, $x1, $x2, $x3
-
; CHECK-LABEL: name: test_scalar_xor_small
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
@@ -31,11 +12,12 @@ body: |
; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[XOR]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64)
- %0(s64) = COPY $x0
- %1(s64) = COPY $x1
- %2(s8) = G_TRUNC %0
- %3(s8) = G_TRUNC %1
- %4(s8) = G_XOR %2, %3
- %5(s64) = G_ANYEXT %4
- $x0 = COPY %5
+ %0:_(s64) = COPY $x0
+ %1:_(s64) = COPY $x1
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_XOR %2, %3
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x0 = COPY %5(s64)
+
...
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir?rev=346253&r1=346252&r2=346253&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/legalize-zextload.mir Tue Nov 6 10:59:18 2018
@@ -1,24 +1,15 @@
-# RUN: llc -O0 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
-
---- |
- target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
- target triple = "aarch64--"
- define void @test_sextload(i8* %addr) {
- entry:
- ret void
- }
-...
-
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
---
-name: test_sextload
+name: test_zextload
body: |
bb.0.entry:
liveins: $x0
- ; CHECK-LABEL: name: test_sextload
- ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
- ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK-LABEL: name: test_zextload
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 1)
+ ; CHECK: $w0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $x0
- %1:_(s32) = G_ZEXTLOAD %0 :: (load 1 from %ir.addr)
+ %1:_(s32) = G_ZEXTLOAD %0 :: (load 1)
$w0 = COPY %1
...
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