[PATCH] D54128: Fix MachineInstr::findRegisterUseOperandIdx subreg checks

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
rampitec added reviewers: nhaehnle, junbuml, sbaranga, sdardis.
Herald added subscribers: jfb, atanasyan, jrtc27, kristof.beyls, arichardson, javed.absar, jvesely.

Operands of isSubRegister were swapped so function did not really
detect subreg reads on physregs. In particular MI->readsRegister()
is broken.

The change affects ARM, MIPS and AArch64 tests:

  LLVM :: CodeGen/AArch64/post-ra-machine-sink.mir
  LLVM :: CodeGen/ARM/deps-fix.ll
  LLVM :: CodeGen/Mips/atomic64.ll
  LLVM :: CodeGen/Mips/compactbranches/compact-branches-64.ll

I have corrected these as I could but I would appreciate if people familiar with these targets check it.


Repository:
  rL LLVM

https://reviews.llvm.org/D54128

Files:
  lib/CodeGen/MachineInstr.cpp
  test/CodeGen/AArch64/post-ra-machine-sink.mir
  test/CodeGen/AMDGPU/optimize-if-exec-masking.mir
  test/CodeGen/ARM/deps-fix.ll
  test/CodeGen/Mips/atomic64.ll
  test/CodeGen/Mips/compactbranches/compact-branches-64.ll

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