[PATCH] D54094: [ARM] Turn assert into condition in ARMCGP

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This revision was automatically updated to reflect the committed changes.
Closed by commit rL346126: [ARM] Turn assert into condition in ARMCGP (authored by sam_parker, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D54094?vs=172555&id=172562#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D54094

Files:
  llvm/trunk/lib/Target/ARM/ARMCodeGenPrepare.cpp
  llvm/trunk/test/CodeGen/ARM/CGP/arm-cgp-icmps.ll


Index: llvm/trunk/test/CodeGen/ARM/CGP/arm-cgp-icmps.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/CGP/arm-cgp-icmps.ll
+++ llvm/trunk/test/CodeGen/ARM/CGP/arm-cgp-icmps.ll
@@ -310,3 +310,23 @@
   ret i32 %conv1
 }
 
+; CHECK-COMMON-LABEL: mul_with_neg_imm
+; CHECK-COMMON-NOT: uxtb
+; CHECK-COMMON:     and [[BIT0:r[0-9]+]], r0, #1
+; CHECK-COMMON:     add.w [[MUL32:r[0-9]+]], [[BIT0]], [[BIT0]], lsl #5
+; CHECK-COMMON:     cmp.w r0, [[MUL32]], lsl #2
+define void @mul_with_neg_imm(i32, i32* %b) {
+entry:
+  %1 = trunc i32 %0 to i8
+  %2 = and i8 %1, 1
+  %conv.i = mul nuw i8 %2, -124
+  %tobool = icmp eq i8 %conv.i, 0
+  br i1 %tobool, label %if.end, label %if.then
+
+if.then:
+  store i32 0, i32* %b, align 4
+  br label %if.end
+
+if.end:
+  ret void
+}
Index: llvm/trunk/lib/Target/ARM/ARMCodeGenPrepare.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeGenPrepare.cpp
+++ llvm/trunk/lib/Target/ARM/ARMCodeGenPrepare.cpp
@@ -443,7 +443,7 @@
   //   > The operators that can wrap are: add, sub, mul and shl.
   //   > shl interprets its second operand as unsigned and if the first operand
   //     is an immediate, it will need zext to be nuw.
-  //   > I'm assuming mul cannot be nuw while using a negative immediate...
+  //   > I'm assuming mul has to interpret immediates as unsigned for nuw.
   //   > Which leaves the nuw add and sub to be handled; as with shl, if an
   //     immediate is used as operand 0, it will need zext to be nuw.
   // - We also allow add and sub to safely overflow in certain circumstances
@@ -468,8 +468,8 @@
           break;
 
         unsigned Opc = I->getOpcode();
-        assert((Opc == Instruction::Add || Opc == Instruction::Sub) &&
-               "expected only an add or sub to use a negative imm");
+        if (Opc != Instruction::Add && Opc != Instruction::Sub)
+          continue;
 
         LLVM_DEBUG(dbgs() << "ARM CGP: Adjusting " << *I << "\n");
         auto *NewConst = ConstantInt::get(Ctx, Const->getValue().abs());


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