[PATCH] D54093: [RISCV] Lower inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill created this revision.
lewis-revill added a reviewer: asb.
Herald added subscribers: llvm-commits, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, eraman.

This validates and lowers arguments to inline asm nodes which have the constraints I, J & K, with the following semantics (equivalent to GCC):

      

I: Any 12-bit signed immediate.
J: Immediate integer zero only.
K: Any 5-bit unsigned immediate.

Note that GCC also implements 'f' for floating point register and 'A' for address-only operand. These are not implemented here because:

1. It appears trivial to implement the floating point register constraint, however since floating point registers are not recognised by the calling convention the call to the inline asm node cannot be lowered.
2. I'm not yet certain how to implement an 'address-only' operand and I'd rather get the above constraints done first and add it later.


Repository:
  rL LLVM

https://reviews.llvm.org/D54093

Files:
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/RISCV/inline-asm.ll

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