[PATCH] D54050: RegisterCoalescer: Report impossible for erasable implicit defs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: MatzeB, kparzysz.
Herald added subscribers: tpr, nhaehnle, wdng, jvesely, qcolombet.

When mapValues was called on one half, this was reporting CR_Erase.
 For the second value, it would see the value live out of the block
and report CR_Impossible. Check if it's live out when clearing
ErasableImplicitDef to avoid reporting inconsistent results.

      

I'm not very confident this is the right way to fix this. Changing
ErasableImplicitDef in the middle of this seems strange to me.


https://reviews.llvm.org/D54050

Files:
  lib/CodeGen/RegisterCoalescer.cpp
  test/CodeGen/AMDGPU/pytorch-cannot-join-subrange.mir


Index: test/CodeGen/AMDGPU/pytorch-cannot-join-subrange.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/pytorch-cannot-join-subrange.mir
@@ -0,0 +1,33 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-coalescing -run-pass=simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: couldnt_join_subrange_live_out_implicit_def
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: couldnt_join_subrange_live_out_implicit_def
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK: bb.1:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   undef %1.sub0:sreg_64_xexec = IMPLICIT_DEF
+  ; CHECK:   S_BRANCH %bb.2
+  ; CHECK: bb.2:
+  ; CHECK:   S_ENDPGM implicit %1
+  bb.0:
+    successors: %bb.1
+
+    undef %0.sub0:sreg_64_xexec = IMPLICIT_DEF
+
+  bb.1:
+    successors: %bb.2
+
+    %1:sreg_64 = COPY %0:sreg_64_xexec
+    %0.sub1:sreg_64_xexec = COPY %0.sub0:sreg_64_xexec
+    S_BRANCH %bb.2
+
+  bb.2:
+    dead %2:sreg_32_xm0 = COPY %0.sub0:sreg_64_xexec
+    S_ENDPGM implicit killed %1
+
+...
Index: lib/CodeGen/RegisterCoalescer.cpp
===================================================================
--- lib/CodeGen/RegisterCoalescer.cpp
+++ lib/CodeGen/RegisterCoalescer.cpp
@@ -2571,6 +2571,10 @@
                       << printMBBReference(*DefMI->getParent())
                       << ", keeping it.\n");
     OtherV.ErasableImplicitDef = false;
+
+    MachineBasicBlock *MBB = Indexes->getMBBFromIndex(V.OtherVNI->def);
+    if (OtherLRQ.endPoint() >= Indexes->getMBBEndIdx(MBB))
+      return CR_Impossible;
   }
 
   // Allow overlapping PHI values. Any real interference would show up in a


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