[PATCH] D54042: [AMDGPU] Extend the SI Load/Store optimizer to combine more things.
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 2 13:41:58 PDT 2018
arsenm added a comment.
My original intent with this pass was to handle the non-adjacent DS writes, with a goal of someday merging to x8 and x16 loads when known from better register pressure information at this later point
Repository:
rL LLVM
https://reviews.llvm.org/D54042
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