[PATCH] D54005: AMDGPU: Fix assertion with bitcast from i64 constant to v4i16

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, kzhuravl.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely.

https://reviews.llvm.org/D54005

Files:
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  test/CodeGen/AMDGPU/bitcast-constant-to-vector.ll


Index: test/CodeGen/AMDGPU/bitcast-constant-to-vector.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/bitcast-constant-to-vector.ll
@@ -0,0 +1,39 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; FIXME: Merge stores
+; GCN-LABEL: {{^}}cast_constant_i64_to_build_vector_v4i16:
+; GCN: global_store_dwordx2
+; GCN: global_store_dword v
+; GCN: global_store_short
+define amdgpu_kernel void @cast_constant_i64_to_build_vector_v4i16(i8 addrspace(1)* nocapture %data) {
+entry:
+  store i8 72, i8 addrspace(1)* %data, align 1
+  %arrayidx1 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 1
+  store i8 101, i8 addrspace(1)* %arrayidx1, align 1
+  %arrayidx2 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 2
+  store i8 108, i8 addrspace(1)* %arrayidx2, align 1
+  %arrayidx3 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 3
+  store i8 108, i8 addrspace(1)* %arrayidx3, align 1
+  %arrayidx4 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 4
+  store i8 111, i8 addrspace(1)* %arrayidx4, align 1
+  %arrayidx5 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 5
+  store i8 44, i8 addrspace(1)* %arrayidx5, align 1
+  %arrayidx6 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 6
+  store i8 32, i8 addrspace(1)* %arrayidx6, align 1
+  %arrayidx7 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 7
+  store i8 87, i8 addrspace(1)* %arrayidx7, align 1
+  %arrayidx8 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 8
+  store i8 111, i8 addrspace(1)* %arrayidx8, align 1
+  %arrayidx9 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 9
+  store i8 114, i8 addrspace(1)* %arrayidx9, align 1
+  %arrayidx10 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 10
+  store i8 108, i8 addrspace(1)* %arrayidx10, align 1
+  %arrayidx11 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 11
+  store i8 100, i8 addrspace(1)* %arrayidx11, align 1
+  %arrayidx12 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 12
+  store i8 33, i8 addrspace(1)* %arrayidx12, align 1
+  %arrayidx13 = getelementptr inbounds i8, i8 addrspace(1)* %data, i64 13
+  store i8 72, i8 addrspace(1)* %arrayidx13, align 1
+  ret void
+}
+
Index: lib/Target/AMDGPU/AMDGPUISelLowering.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -3817,9 +3817,10 @@
       if (Src.getValueType() == MVT::i64) {
         SDLoc SL(N);
         uint64_t CVal = C->getZExtValue();
-        return DAG.getNode(ISD::BUILD_VECTOR, SL, DestVT,
-                           DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
-                           DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
+        SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
+                                 DAG.getConstant(Lo_32(CVal), SL, MVT::i32),
+                                 DAG.getConstant(Hi_32(CVal), SL, MVT::i32));
+        return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);
       }
     }
 


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