[PATCH] D50633: [AMDGPU] Add new Mode Register pass

[Brian Sumner via Phabricator via llvm-commits]

b-sumner added a comment.

One thing we've wanted for compute for quite a while now is a way to request non-default-rounded add, sub, mul, div, fma, and sqrt.  Assuming we ever figure out how to represent these in the IR, ideally without falling back on intrinsics, could this approach be used to implement and minimize the mode changes for those as well?


Repository:
  rL LLVM

https://reviews.llvm.org/D50633