[llvm] r345786 - [AArch64] Sort switch cases (NFC)
Evandro Menezes via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 31 14:56:49 PDT 2018
Author: evandro
Date: Wed Oct 31 14:56:49 2018
New Revision: 345786
URL: http://llvm.org/viewvc/llvm-project?rev=345786&view=rev
Log:
[AArch64] Sort switch cases (NFC)
Modified:
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp?rev=345786&r1=345785&r2=345786&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.cpp Wed Oct 31 14:56:49 2018
@@ -67,16 +67,30 @@ void AArch64Subtarget::initializePropert
// this in the future so we can specify it together with the subtarget
// features.
switch (ARMProcFamily) {
+ case Others:
+ break;
+ case CortexA35:
+ break;
+ case CortexA53:
+ PrefFunctionAlignment = 3;
+ break;
+ case CortexA55:
+ break;
+ case CortexA57:
+ MaxInterleaveFactor = 4;
+ PrefFunctionAlignment = 4;
+ break;
+ case CortexA72:
+ case CortexA73:
+ case CortexA75:
+ PrefFunctionAlignment = 4;
+ break;
case Cyclone:
CacheLineSize = 64;
PrefetchDistance = 280;
MinPrefetchStride = 2048;
MaxPrefetchIterationsAhead = 3;
break;
- case CortexA57:
- MaxInterleaveFactor = 4;
- PrefFunctionAlignment = 4;
- break;
case ExynosM1:
MaxInterleaveFactor = 4;
MaxJumpTableSize = 8;
@@ -98,11 +112,6 @@ void AArch64Subtarget::initializePropert
MinPrefetchStride = 2048;
MaxPrefetchIterationsAhead = 8;
break;
- case Saphira:
- MaxInterleaveFactor = 4;
- // FIXME: remove this to enable 64-bit SLP if performance looks good.
- MinVectorRegisterBitWidth = 128;
- break;
case Kryo:
MaxInterleaveFactor = 4;
VectorInsertExtractBaseCost = 2;
@@ -113,6 +122,11 @@ void AArch64Subtarget::initializePropert
// FIXME: remove this to enable 64-bit SLP if performance looks good.
MinVectorRegisterBitWidth = 128;
break;
+ case Saphira:
+ MaxInterleaveFactor = 4;
+ // FIXME: remove this to enable 64-bit SLP if performance looks good.
+ MinVectorRegisterBitWidth = 128;
+ break;
case ThunderX2T99:
CacheLineSize = 64;
PrefFunctionAlignment = 3;
@@ -134,17 +148,6 @@ void AArch64Subtarget::initializePropert
// FIXME: remove this to enable 64-bit SLP if performance looks good.
MinVectorRegisterBitWidth = 128;
break;
- case CortexA35: break;
- case CortexA53:
- PrefFunctionAlignment = 3;
- break;
- case CortexA55: break;
- case CortexA72:
- case CortexA73:
- case CortexA75:
- PrefFunctionAlignment = 4;
- break;
- case Others: break;
}
}
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