[llvm] r345782 - [ARM] Add missing pseudo-instruction for Thumb1 RSBS.
Eli Friedman via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 31 14:45:48 PDT 2018
Author: efriedma
Date: Wed Oct 31 14:45:48 2018
New Revision: 345782
URL: http://llvm.org/viewvc/llvm-project?rev=345782&view=rev
Log:
[ARM] Add missing pseudo-instruction for Thumb1 RSBS.
Shows up rarely for 64-bit arithmetic, more frequently for the compare
patterns added in r325323.
Differential Revision: https://reviews.llvm.org/D53848
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/test/CodeGen/ARM/and-load-combine.ll
llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll
llvm/trunk/test/CodeGen/ARM/select-imm.ll
llvm/trunk/test/CodeGen/ARM/smml.ll
llvm/trunk/test/CodeGen/Thumb/branchless-cmp.ll
llvm/trunk/test/CodeGen/Thumb/long-setcc.ll
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=345782&r1=345781&r2=345782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Oct 31 14:45:48 2018
@@ -2199,6 +2199,7 @@ static const AddSubFlagsOpcodePair AddSu
{ARM::tSUBSi8, ARM::tSUBi8},
{ARM::tSUBSrr, ARM::tSUBrr},
{ARM::tSBCS, ARM::tSBC},
+ {ARM::tRSBS, ARM::tRSB},
{ARM::t2ADDSri, ARM::t2ADDri},
{ARM::t2ADDSrr, ARM::t2ADDrr},
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=345782&r1=345781&r2=345782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Oct 31 14:45:48 2018
@@ -1343,6 +1343,12 @@ let hasPostISelHook = 1, Defs = [CPSR] i
tGPR:$Rm))]>,
Requires<[IsThumb1Only]>,
Sched<[WriteALU]>;
+
+ def tRSBS : tPseudoInst<(outs tGPR:$Rd), (ins tGPR:$Rn),
+ 2, IIC_iALUr,
+ [(set tGPR:$Rd, CPSR, (ARMsubc 0, tGPR:$Rn))]>,
+ Requires<[IsThumb1Only]>,
+ Sched<[WriteALU]>;
}
// Sign-extend byte
Modified: llvm/trunk/test/CodeGen/ARM/and-load-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/and-load-combine.ll?rev=345782&r1=345781&r2=345782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/and-load-combine.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/and-load-combine.ll Wed Oct 31 14:45:48 2018
@@ -28,8 +28,7 @@ define arm_aapcscc zeroext i1 @cmp_xor8_
; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: eors r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -74,8 +73,7 @@ define arm_aapcscc zeroext i1 @cmp_xor8_
; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: eors r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -121,8 +119,7 @@ define arm_aapcscc zeroext i1 @cmp_xor8_
; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: eors r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -167,8 +164,7 @@ define arm_aapcscc zeroext i1 @cmp_xor16
; THUMB1-NEXT: ldrh r0, [r0]
; THUMB1-NEXT: ldrh r1, [r1]
; THUMB1-NEXT: eors r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -213,8 +209,7 @@ define arm_aapcscc zeroext i1 @cmp_or8_s
; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: orrs r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -259,8 +254,7 @@ define arm_aapcscc zeroext i1 @cmp_or8_s
; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: orrs r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -306,8 +300,7 @@ define arm_aapcscc zeroext i1 @cmp_or8_i
; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: orrs r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -352,8 +345,7 @@ define arm_aapcscc zeroext i1 @cmp_or16(
; THUMB1-NEXT: ldrh r0, [r0]
; THUMB1-NEXT: ldrh r1, [r1]
; THUMB1-NEXT: orrs r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -398,8 +390,7 @@ define arm_aapcscc zeroext i1 @cmp_and8_
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: ldrb r2, [r0]
; THUMB1-NEXT: ands r2, r1
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r2
+; THUMB1-NEXT: rsbs r0, r2, #0
; THUMB1-NEXT: adcs r0, r2
; THUMB1-NEXT: bx lr
;
@@ -444,8 +435,7 @@ define arm_aapcscc zeroext i1 @cmp_and8_
; THUMB1-NEXT: ldrb r0, [r0]
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: ands r1, r0
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -491,8 +481,7 @@ define arm_aapcscc zeroext i1 @cmp_and8_
; THUMB1-NEXT: ldrb r1, [r1]
; THUMB1-NEXT: ldrb r2, [r0]
; THUMB1-NEXT: ands r2, r1
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r2
+; THUMB1-NEXT: rsbs r0, r2, #0
; THUMB1-NEXT: adcs r0, r2
; THUMB1-NEXT: bx lr
;
@@ -537,8 +526,7 @@ define arm_aapcscc zeroext i1 @cmp_and16
; THUMB1-NEXT: ldrh r1, [r1]
; THUMB1-NEXT: ldrh r2, [r0]
; THUMB1-NEXT: ands r2, r1
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r2
+; THUMB1-NEXT: rsbs r0, r2, #0
; THUMB1-NEXT: adcs r0, r2
; THUMB1-NEXT: bx lr
;
@@ -881,8 +869,7 @@ define arm_aapcscc i1 @test6(i8* %x, i8
; THUMB1-NEXT: ands r0, r1
; THUMB1-NEXT: uxtb r1, r2
; THUMB1-NEXT: subs r1, r0, r1
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
@@ -929,8 +916,7 @@ define arm_aapcscc i1 @test7(i16* %x, i1
; THUMB1-NEXT: ands r0, r1
; THUMB1-NEXT: uxtb r1, r2
; THUMB1-NEXT: subs r1, r0, r1
-; THUMB1-NEXT: movs r0, #0
-; THUMB1-NEXT: subs r0, r0, r1
+; THUMB1-NEXT: rsbs r0, r1, #0
; THUMB1-NEXT: adcs r0, r1
; THUMB1-NEXT: bx lr
;
Modified: llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll?rev=345782&r1=345781&r2=345782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/atomic-cmpxchg.ll Wed Oct 31 14:45:48 2018
@@ -24,8 +24,7 @@ entry:
; CHECK-THUMB: bl __sync_val_compare_and_swap_1
; CHECK-THUMB-NOT: mov [[R1:r[0-7]]], r0
; CHECK-THUMB: subs [[R1:r[0-7]]], r0, {{r[0-9]+}}
-; CHECK-THUMB: movs r0, #0
-; CHECK-THUMB: subs r0, r0, [[R1]]
+; CHECK-THUMB: rsbs r0, [[R1]], #0
; CHECK-THUMB: adcs r0, [[R1]]
; CHECK-ARMV6-LABEL: test_cmpxchg_res_i8:
@@ -47,8 +46,7 @@ entry:
; CHECK-THUMBV6-NEXT: bl __sync_val_compare_and_swap_1
; CHECK-THUMBV6-NEXT: uxtb r1, r4
; CHECK-THUMBV6-NEXT: subs [[R1:r[0-7]]], r0, {{r[0-9]+}}
-; CHECK-THUMBV6-NEXT: movs r0, #0
-; CHECK-THUMBV6-NEXT: subs r0, r0, [[R1]]
+; CHECK-THUMBV6-NEXT: rsbs r0, [[R1]], #0
; CHECK-THUMBV6-NEXT: adcs r0, [[R1]]
; CHECK-ARMV7-LABEL: test_cmpxchg_res_i8:
Modified: llvm/trunk/test/CodeGen/ARM/select-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select-imm.ll?rev=345782&r1=345781&r2=345782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select-imm.ll Wed Oct 31 14:45:48 2018
@@ -71,8 +71,7 @@ entry:
; ARMT2: lsr r0, r0, #5
; THUMB1-LABEL: t3:
-; THUMB1: movs r1, #0
-; THUMB1: subs r1, r1, r0
+; THUMB1: rsbs r1, r0, #0
; THUMB1: adcs r0, r1
; THUMB2-LABEL: t3:
@@ -116,8 +115,7 @@ entry:
; THUMB1-LABEL: t5:
; THUMB1-NOT: bne
-; THUMB1: movs r0, #0
-; THUMB1: subs r0, r0, r1
+; THUMB1: rsbs r0, r1, #0
; THUMB1: adcs r0, r1
; THUMB2-LABEL: t5:
@@ -196,8 +194,7 @@ entry:
; THUMB1: bl t7
; THUMB1: mov r1, r0
; THUMB1: subs r2, r4, #5
-; THUMB1: movs r0, #0
-; THUMB1: subs r0, r0, r2
+; THUMB1: rsbs r0, r2, #0
; THUMB1: adcs r0, r2
; THUMB2-LABEL: t8:
@@ -302,8 +299,7 @@ entry:
; ARMT2: lsr r0, r0, #5
; THUMB1-LABEL: t10:
-; THUMB1: movs r0, #0
-; THUMB1: subs r0, r0, r1
+; THUMB1: rsbs r0, r1, #0
; THUMB1: adcs r0, r1
; THUMB2-LABEL: t10:
Modified: llvm/trunk/test/CodeGen/ARM/smml.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/smml.ll?rev=345782&r1=345781&r2=345782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/smml.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/smml.ll Wed Oct 31 14:45:48 2018
@@ -44,7 +44,7 @@ declare void @opaque(i32)
define void @test_used_flags(i32 %in1, i32 %in2) {
; CHECK-LABEL: test_used_flags:
; CHECK-THUMB: movs r2, #0
-; CHECK-THUMB: subs r0, r2, r0
+; CHECK-THUMB: rsbs r0, r0, #0
; CHECK-THUMB: sbcs r2, r1
; CHECK-THUMB: bge
; CHECK-V6: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
Modified: llvm/trunk/test/CodeGen/Thumb/branchless-cmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/branchless-cmp.ll?rev=345782&r1=345781&r2=345782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/branchless-cmp.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/branchless-cmp.ll Wed Oct 31 14:45:48 2018
@@ -20,8 +20,7 @@ entry:
; CHECK-LABEL: test1b:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r1, r0, r1
-; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: subs r0, r0, r1
+; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: adcs r0, r1
}
@@ -33,8 +32,7 @@ entry:
; CHECK-LABEL: test2a:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r1, r0, r1
-; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: subs r0, r0, r1
+; CHECK-NEXT: rsbs r0, r1, #0
; CHECK-NEXT: adcs r0, r1
}
@@ -71,8 +69,7 @@ entry:
; CHECK-LABEL: test3b:
; CHECK-NOT: b{{(ne)|(eq)}}
; CHECK: subs r0, r0, r1
-; CHECK-NEXT: movs r1, #0
-; CHECK-NEXT: subs r1, r1, r0
+; CHECK-NEXT: rsbs r1, r0, #0
; CHECK-NEXT: adcs r1, r0
; CHECK-NEXT: lsls r0, r1, #2
}
Modified: llvm/trunk/test/CodeGen/Thumb/long-setcc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/long-setcc.ll?rev=345782&r1=345781&r2=345782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/long-setcc.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb/long-setcc.ll Wed Oct 31 14:45:48 2018
@@ -9,8 +9,7 @@ define i1 @t1(i64 %x) {
define i1 @t2(i64 %x) {
; CHECK-LABEL: t2:
-; CHECK: movs r0, #0
-; CHECK: subs r0, r0, r1
+; CHECK: rsbs r0, r1, #0
; CHECK: adcs r0, r1
%tmp = icmp ult i64 %x, 4294967296
ret i1 %tmp
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