[llvm] r345721 - [DAGCombiner] Fold 0 div/rem X to 0
David Bolvansky via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 31 07:18:57 PDT 2018
Author: xbolva00
Date: Wed Oct 31 07:18:57 2018
New Revision: 345721
URL: http://llvm.org/viewvc/llvm-project?rev=345721&view=rev
Log:
[DAGCombiner] Fold 0 div/rem X to 0
Reviewers: RKSimon, spatel, javed.absar, craig.topper, t.p.northover
Reviewed By: RKSimon
Subscribers: craig.topper, llvm-commits
Differential Revision: https://reviews.llvm.org/D52504
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
llvm/trunk/test/CodeGen/X86/combine-srem.ll
llvm/trunk/test/CodeGen/X86/combine-udiv.ll
llvm/trunk/test/CodeGen/X86/combine-urem.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=345721&r1=345720&r2=345721&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Oct 31 07:18:57 2018
@@ -3128,8 +3128,11 @@ static SDValue simplifyDivRem(SDNode *N,
if (N0.isUndef())
return DAG.getConstant(0, DL, VT);
- // TODO: 0 / X -> 0
- // TODO: 0 % X -> 0
+ // 0 / X -> 0
+ // 0 % X -> 0
+ ConstantSDNode *N0C = isConstOrConstSplat(N0);
+ if (N0C && N0C->isNullValue())
+ return N0;
// X / X -> 1
// X % X -> 0
Modified: llvm/trunk/test/CodeGen/X86/combine-sdiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-sdiv.ll?rev=345721&r1=345720&r2=345721&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-sdiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-sdiv.ll Wed Oct 31 07:18:57 2018
@@ -107,99 +107,25 @@ define <4 x i32> @combine_vec_sdiv_by_mi
ret <4 x i32> %1
}
-; TODO fold (sdiv 0, x) -> 0
+; fold (sdiv 0, x) -> 0
define i32 @combine_sdiv_zero(i32 %x) {
; CHECK-LABEL: combine_sdiv_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: idivl %edi
; CHECK-NEXT: retq
%1 = sdiv i32 0, %x
ret i32 %1
}
define <4 x i32> @combine_vec_sdiv_zero(<4 x i32> %x) {
-; SSE2-LABEL: combine_vec_sdiv_zero:
-; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
-; SSE2-NEXT: movd %xmm1, %ecx
-; SSE2-NEXT: xorl %eax, %eax
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: idivl %ecx
-; SSE2-NEXT: movd %eax, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
-; SSE2-NEXT: movd %xmm2, %ecx
-; SSE2-NEXT: xorl %eax, %eax
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: idivl %ecx
-; SSE2-NEXT: movd %eax, %xmm2
-; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
-; SSE2-NEXT: movd %xmm0, %ecx
-; SSE2-NEXT: xorl %eax, %eax
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: idivl %ecx
-; SSE2-NEXT: movd %eax, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
-; SSE2-NEXT: movd %xmm0, %ecx
-; SSE2-NEXT: xorl %eax, %eax
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: idivl %ecx
-; SSE2-NEXT: movd %eax, %xmm0
-; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; SSE2-NEXT: movdqa %xmm1, %xmm0
-; SSE2-NEXT: retq
-;
-; SSE41-LABEL: combine_vec_sdiv_zero:
-; SSE41: # %bb.0:
-; SSE41-NEXT: pextrd $1, %xmm0, %ecx
-; SSE41-NEXT: xorl %eax, %eax
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: idivl %ecx
-; SSE41-NEXT: movl %eax, %ecx
-; SSE41-NEXT: movd %xmm0, %esi
-; SSE41-NEXT: xorl %eax, %eax
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: idivl %esi
-; SSE41-NEXT: movd %eax, %xmm1
-; SSE41-NEXT: pinsrd $1, %ecx, %xmm1
-; SSE41-NEXT: pextrd $2, %xmm0, %ecx
-; SSE41-NEXT: xorl %eax, %eax
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: idivl %ecx
-; SSE41-NEXT: pinsrd $2, %eax, %xmm1
-; SSE41-NEXT: pextrd $3, %xmm0, %ecx
-; SSE41-NEXT: xorl %eax, %eax
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: idivl %ecx
-; SSE41-NEXT: pinsrd $3, %eax, %xmm1
-; SSE41-NEXT: movdqa %xmm1, %xmm0
-; SSE41-NEXT: retq
+; SSE-LABEL: combine_vec_sdiv_zero:
+; SSE: # %bb.0:
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_sdiv_zero:
; AVX: # %bb.0:
-; AVX-NEXT: vpextrd $1, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl %ecx
-; AVX-NEXT: movl %eax, %ecx
-; AVX-NEXT: vmovd %xmm0, %esi
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl %esi
-; AVX-NEXT: vmovd %eax, %xmm1
-; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
-; AVX-NEXT: vpextrd $2, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl %ecx
-; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
-; AVX-NEXT: vpextrd $3, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl %ecx
-; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = sdiv <4 x i32> zeroinitializer, %x
ret <4 x i32> %1
Modified: llvm/trunk/test/CodeGen/X86/combine-srem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-srem.ll?rev=345721&r1=345720&r2=345721&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-srem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-srem.ll Wed Oct 31 07:18:57 2018
@@ -100,14 +100,11 @@ define <4 x i32> @combine_vec_srem_by_mi
ret <4 x i32> %1
}
-; TODO fold (srem 0, x) -> 0
+; fold (srem 0, x) -> 0
define i32 @combine_srem_zero(i32 %x) {
; CHECK-LABEL: combine_srem_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: idivl %edi
-; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: retq
%1 = srem i32 0, %x
ret i32 %1
@@ -116,53 +113,12 @@ define i32 @combine_srem_zero(i32 %x) {
define <4 x i32> @combine_vec_srem_zero(<4 x i32> %x) {
; SSE-LABEL: combine_vec_srem_zero:
; SSE: # %bb.0:
-; SSE-NEXT: pextrd $1, %xmm0, %ecx
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: idivl %ecx
-; SSE-NEXT: movl %edx, %ecx
-; SSE-NEXT: movd %xmm0, %esi
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: idivl %esi
-; SSE-NEXT: movd %edx, %xmm1
-; SSE-NEXT: pinsrd $1, %ecx, %xmm1
-; SSE-NEXT: pextrd $2, %xmm0, %ecx
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: idivl %ecx
-; SSE-NEXT: pinsrd $2, %edx, %xmm1
-; SSE-NEXT: pextrd $3, %xmm0, %ecx
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: idivl %ecx
-; SSE-NEXT: pinsrd $3, %edx, %xmm1
-; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_srem_zero:
; AVX: # %bb.0:
-; AVX-NEXT: vpextrd $1, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl %ecx
-; AVX-NEXT: movl %edx, %ecx
-; AVX-NEXT: vmovd %xmm0, %esi
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl %esi
-; AVX-NEXT: vmovd %edx, %xmm1
-; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
-; AVX-NEXT: vpextrd $2, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl %ecx
-; AVX-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
-; AVX-NEXT: vpextrd $3, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: idivl %ecx
-; AVX-NEXT: vpinsrd $3, %edx, %xmm1, %xmm0
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = srem <4 x i32> zeroinitializer, %x
ret <4 x i32> %1
Modified: llvm/trunk/test/CodeGen/X86/combine-udiv.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-udiv.ll?rev=345721&r1=345720&r2=345721&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-udiv.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-udiv.ll Wed Oct 31 07:18:57 2018
@@ -90,124 +90,30 @@ define <4 x i32> @combine_vec_udiv_by_mi
ret <4 x i32> %1
}
-; TODO fold (udiv 0, x) -> 0
+; fold (udiv 0, x) -> 0
define i32 @combine_udiv_zero(i32 %x) {
; CHECK-LABEL: combine_udiv_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %edi
; CHECK-NEXT: retq
%1 = udiv i32 0, %x
ret i32 %1
}
define <4 x i32> @combine_vec_udiv_zero(<4 x i32> %x) {
-; SSE2-LABEL: combine_vec_udiv_zero:
-; SSE2: # %bb.0:
-; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,1,2,3]
-; SSE2-NEXT: movd %xmm1, %ecx
-; SSE2-NEXT: xorl %eax, %eax
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %eax, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
-; SSE2-NEXT: movd %xmm2, %ecx
-; SSE2-NEXT: xorl %eax, %eax
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %eax, %xmm2
-; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
-; SSE2-NEXT: movd %xmm0, %ecx
-; SSE2-NEXT: xorl %eax, %eax
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %eax, %xmm1
-; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
-; SSE2-NEXT: movd %xmm0, %ecx
-; SSE2-NEXT: xorl %eax, %eax
-; SSE2-NEXT: xorl %edx, %edx
-; SSE2-NEXT: divl %ecx
-; SSE2-NEXT: movd %eax, %xmm0
-; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
-; SSE2-NEXT: movdqa %xmm1, %xmm0
-; SSE2-NEXT: retq
-;
-; SSE41-LABEL: combine_vec_udiv_zero:
-; SSE41: # %bb.0:
-; SSE41-NEXT: pextrd $1, %xmm0, %ecx
-; SSE41-NEXT: xorl %eax, %eax
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
-; SSE41-NEXT: movl %eax, %ecx
-; SSE41-NEXT: movd %xmm0, %esi
-; SSE41-NEXT: xorl %eax, %eax
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %esi
-; SSE41-NEXT: movd %eax, %xmm1
-; SSE41-NEXT: pinsrd $1, %ecx, %xmm1
-; SSE41-NEXT: pextrd $2, %xmm0, %ecx
-; SSE41-NEXT: xorl %eax, %eax
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
-; SSE41-NEXT: pinsrd $2, %eax, %xmm1
-; SSE41-NEXT: pextrd $3, %xmm0, %ecx
-; SSE41-NEXT: xorl %eax, %eax
-; SSE41-NEXT: xorl %edx, %edx
-; SSE41-NEXT: divl %ecx
-; SSE41-NEXT: pinsrd $3, %eax, %xmm1
-; SSE41-NEXT: movdqa %xmm1, %xmm0
-; SSE41-NEXT: retq
+; SSE-LABEL: combine_vec_udiv_zero:
+; SSE: # %bb.0:
+; SSE-NEXT: xorps %xmm0, %xmm0
+; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_udiv_zero:
; AVX: # %bb.0:
-; AVX-NEXT: vpextrd $1, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %ecx
-; AVX-NEXT: movl %eax, %ecx
-; AVX-NEXT: vmovd %xmm0, %esi
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %esi
-; AVX-NEXT: vmovd %eax, %xmm1
-; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
-; AVX-NEXT: vpextrd $2, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %ecx
-; AVX-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
-; AVX-NEXT: vpextrd $3, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %ecx
-; AVX-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
;
; XOP-LABEL: combine_vec_udiv_zero:
; XOP: # %bb.0:
-; XOP-NEXT: vpextrd $1, %xmm0, %ecx
-; XOP-NEXT: xorl %eax, %eax
-; XOP-NEXT: xorl %edx, %edx
-; XOP-NEXT: divl %ecx
-; XOP-NEXT: movl %eax, %ecx
-; XOP-NEXT: vmovd %xmm0, %esi
-; XOP-NEXT: xorl %eax, %eax
-; XOP-NEXT: xorl %edx, %edx
-; XOP-NEXT: divl %esi
-; XOP-NEXT: vmovd %eax, %xmm1
-; XOP-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
-; XOP-NEXT: vpextrd $2, %xmm0, %ecx
-; XOP-NEXT: xorl %eax, %eax
-; XOP-NEXT: xorl %edx, %edx
-; XOP-NEXT: divl %ecx
-; XOP-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
-; XOP-NEXT: vpextrd $3, %xmm0, %ecx
-; XOP-NEXT: xorl %eax, %eax
-; XOP-NEXT: xorl %edx, %edx
-; XOP-NEXT: divl %ecx
-; XOP-NEXT: vpinsrd $3, %eax, %xmm1, %xmm0
+; XOP-NEXT: vxorps %xmm0, %xmm0, %xmm0
; XOP-NEXT: retq
%1 = udiv <4 x i32> zeroinitializer, %x
ret <4 x i32> %1
Modified: llvm/trunk/test/CodeGen/X86/combine-urem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-urem.ll?rev=345721&r1=345720&r2=345721&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/combine-urem.ll (original)
+++ llvm/trunk/test/CodeGen/X86/combine-urem.ll Wed Oct 31 07:18:57 2018
@@ -89,14 +89,11 @@ define <4 x i32> @combine_vec_urem_by_mi
ret <4 x i32> %1
}
-; TODO fold (urem 0, x) -> 0
+; fold (urem 0, x) -> 0
define i32 @combine_urem_zero(i32 %x) {
; CHECK-LABEL: combine_urem_zero:
; CHECK: # %bb.0:
; CHECK-NEXT: xorl %eax, %eax
-; CHECK-NEXT: xorl %edx, %edx
-; CHECK-NEXT: divl %edi
-; CHECK-NEXT: movl %edx, %eax
; CHECK-NEXT: retq
%1 = urem i32 0, %x
ret i32 %1
@@ -105,53 +102,12 @@ define i32 @combine_urem_zero(i32 %x) {
define <4 x i32> @combine_vec_urem_zero(<4 x i32> %x) {
; SSE-LABEL: combine_vec_urem_zero:
; SSE: # %bb.0:
-; SSE-NEXT: pextrd $1, %xmm0, %ecx
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
-; SSE-NEXT: movl %edx, %ecx
-; SSE-NEXT: movd %xmm0, %esi
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %esi
-; SSE-NEXT: movd %edx, %xmm1
-; SSE-NEXT: pinsrd $1, %ecx, %xmm1
-; SSE-NEXT: pextrd $2, %xmm0, %ecx
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
-; SSE-NEXT: pinsrd $2, %edx, %xmm1
-; SSE-NEXT: pextrd $3, %xmm0, %ecx
-; SSE-NEXT: xorl %eax, %eax
-; SSE-NEXT: xorl %edx, %edx
-; SSE-NEXT: divl %ecx
-; SSE-NEXT: pinsrd $3, %edx, %xmm1
-; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: xorps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_urem_zero:
; AVX: # %bb.0:
-; AVX-NEXT: vpextrd $1, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %ecx
-; AVX-NEXT: movl %edx, %ecx
-; AVX-NEXT: vmovd %xmm0, %esi
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %esi
-; AVX-NEXT: vmovd %edx, %xmm1
-; AVX-NEXT: vpinsrd $1, %ecx, %xmm1, %xmm1
-; AVX-NEXT: vpextrd $2, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %ecx
-; AVX-NEXT: vpinsrd $2, %edx, %xmm1, %xmm1
-; AVX-NEXT: vpextrd $3, %xmm0, %ecx
-; AVX-NEXT: xorl %eax, %eax
-; AVX-NEXT: xorl %edx, %edx
-; AVX-NEXT: divl %ecx
-; AVX-NEXT: vpinsrd $3, %edx, %xmm1, %xmm0
+; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = urem <4 x i32> zeroinitializer, %x
ret <4 x i32> %1
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