[PATCH] D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer added a comment.

Apologies for being late to the party, but I am now looking into this too because we've seen some significant regressions with this change committed.
I am not blaming this commit, not yet, because I haven't fully understood the problem yet. As I am new to this area, it wanted to dump some initial thoughts here (because it takes me some time to get up to speed), perhaps people can comment.

First, we found the change in  test `CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll` a bit suspicious. Latencies are changed from 1, 3, 3, and 4 to:

  ; CHECK-SAME:  Latency=1
  ; CHECK-NEXT:  Data
  ; CHECK-SAME:  Latency=3
  ; CHECK-NEXT:  Data
  ; CHECK-SAME:  Latency=0
  ; CHECK-NEXT:  Data
  ; CHECK-SAME:  Latency=0

The last 2 latencies are changed to 0. We are generating and LDM for this case: `ldm r0!, {r1, r2, r3}`, and I don't see yet why the latency of the last 2 operands are 0s.

This makes us wonder if variadic instructions and instructions with optional defs are ignored/missed in this patch?


https://reviews.llvm.org/D49671