[PATCH] D53877: [IR] Strawman for dedicated FNeg IR instruction

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added inline comments.


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Comment at: include/llvm/Bitcode/LLVMBitCodes.h:346
+  CST_CODE_CE_UNOP = 25,         // CE_UNOP:      [opcode, opval]
 };
 
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It wasn't clear to me if it was safe to reorder these values. Any thoughts on this?


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Comment at: include/llvm/Bitcode/LLVMBitCodes.h:479
   FUNC_CODE_INST_UNREACHABLE = 15, // UNREACHABLE
 
   FUNC_CODE_INST_PHI = 16, // PHI:        [ty, val0,bb0, ...]
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Same thing here about organizing the enum members.


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Comment at: lib/AsmParser/LLParser.cpp:3322
+    return false;
+  }
   // Binary Operators.
----------------
The lexer/parser is another area that I'm not too familiar with. A thorough review would be appreciated.


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Comment at: lib/Bitcode/Reader/BitcodeReader.cpp:2346
+      break;
+    }
     case bitc::CST_CODE_CE_BINOP: {  // CE_BINOP: [opcode, opval, opval]
----------------
I'm not that familiar with the Bitcode format. Any suggestions on the best way to produce a test case for this? Or is it just the obvious, produce bitcode and make sure it works as expected?


Repository:
  rL LLVM

https://reviews.llvm.org/D53877