[llvm] r345560 - AMDGPU: Remove custom BUILD_VECTOR combine
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 29 18:37:59 PDT 2018
Author: arsenm
Date: Mon Oct 29 18:37:59 2018
New Revision: 345560
URL: http://llvm.org/viewvc/llvm-project?rev=345560&view=rev
Log:
AMDGPU: Remove custom BUILD_VECTOR combine
This was looping in a testcase and removing it
now slightly improves a test.
Added:
llvm/trunk/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp?rev=345560&r1=345559&r2=345560&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp Mon Oct 29 18:37:59 2018
@@ -679,7 +679,6 @@ SITargetLowering::SITargetLowering(const
setTargetDAGCombine(ISD::SCALAR_TO_VECTOR);
setTargetDAGCombine(ISD::ZERO_EXTEND);
setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
- setTargetDAGCombine(ISD::BUILD_VECTOR);
// All memory operations. Some folding on the pointer operand is done to help
// matching the constant offsets in the addressing modes.
@@ -8133,48 +8132,6 @@ SDValue SITargetLowering::performExtract
return SDValue();
}
-static bool convertBuildVectorCastElt(SelectionDAG &DAG,
- SDValue &Lo, SDValue &Hi) {
- if (Hi.getOpcode() == ISD::BITCAST &&
- Hi.getOperand(0).getValueType() == MVT::f16 &&
- (isa<ConstantSDNode>(Lo) || Lo.isUndef())) {
- Lo = DAG.getNode(ISD::BITCAST, SDLoc(Lo), MVT::f16, Lo);
- Hi = Hi.getOperand(0);
- return true;
- }
-
- return false;
-}
-
-SDValue SITargetLowering::performBuildVectorCombine(
- SDNode *N, DAGCombinerInfo &DCI) const {
- SDLoc SL(N);
-
- if (!isTypeLegal(MVT::v2i16))
- return SDValue();
- SelectionDAG &DAG = DCI.DAG;
- EVT VT = N->getValueType(0);
-
- if (VT == MVT::v2i16) {
- SDValue Lo = N->getOperand(0);
- SDValue Hi = N->getOperand(1);
-
- // v2i16 build_vector (const|undef), (bitcast f16:$x)
- // -> bitcast (v2f16 build_vector const|undef, $x
- if (convertBuildVectorCastElt(DAG, Lo, Hi)) {
- SDValue NewVec = DAG.getBuildVector(MVT::v2f16, SL, { Lo, Hi });
- return DAG.getNode(ISD::BITCAST, SL, VT, NewVec);
- }
-
- if (convertBuildVectorCastElt(DAG, Hi, Lo)) {
- SDValue NewVec = DAG.getBuildVector(MVT::v2f16, SL, { Hi, Lo });
- return DAG.getNode(ISD::BITCAST, SL, VT, NewVec);
- }
- }
-
- return SDValue();
-}
-
unsigned SITargetLowering::getFusedOpcode(const SelectionDAG &DAG,
const SDNode *N0,
const SDNode *N1) const {
@@ -8783,8 +8740,6 @@ SDValue SITargetLowering::PerformDAGComb
}
case ISD::EXTRACT_VECTOR_ELT:
return performExtractVectorEltCombine(N, DCI);
- case ISD::BUILD_VECTOR:
- return performBuildVectorCombine(N, DCI);
}
return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
}
Modified: llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h?rev=345560&r1=345559&r2=345560&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIISelLowering.h Mon Oct 29 18:37:59 2018
@@ -154,7 +154,6 @@ private:
SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
- SDValue performBuildVectorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
unsigned getFusedOpcode(const SelectionDAG &DAG,
const SDNode *N0, const SDNode *N1) const;
Added: llvm/trunk/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll?rev=345560&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/build-vector-insert-elt-infloop.ll Mon Oct 29 18:37:59 2018
@@ -0,0 +1,27 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+; There was an infinite loop in DAGCombiner from a target build_vector
+; combine and a generic insert_vector_elt combine.
+
+; GCN-LABEL: {{^}}combine_loop:
+; GCN: flat_load_ushort
+; GCN: flat_store_short
+; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
+define amdgpu_kernel void @combine_loop(i16* %arg) #0 {
+bb:
+ br label %bb1
+
+bb1:
+ %tmp = phi <2 x i16> [ <i16 15360, i16 15360>, %bb ], [ %tmp5, %bb1 ]
+ %tmp2 = phi half [ 0xH0000, %bb ], [ %tmp8, %bb1 ]
+ %tmp3 = load volatile half, half* null, align 536870912
+ %tmp4 = bitcast half %tmp3 to i16
+ %tmp5 = insertelement <2 x i16> <i16 0, i16 undef>, i16 %tmp4, i32 1
+ %tmp6 = bitcast i16* %arg to half*
+ store half %tmp2, half* %tmp6, align 2
+ %tmp7 = bitcast <2 x i16> %tmp to <2 x half>
+ %tmp8 = extractelement <2 x half> %tmp7, i32 0
+ br label %bb1
+}
+
+attributes #0 = { nounwind }
Modified: llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll?rev=345560&r1=345559&r2=345560&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/mad-mix-hi.ll Mon Oct 29 18:37:59 2018
@@ -49,9 +49,9 @@ define <2 x half> @v_mad_mixhi_f16_f16lo
}
; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack:
-; GFX9: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2
-; GFX9-NEXT: v_mov_b32_e32 v0, v3
+; GFX9: s_waitcnt
+; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_setpc_b64
define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack(half %src0, half %src1, half %src2) #0 {
%src0.ext = fpext half %src0 to float
@@ -66,9 +66,9 @@ define i32 @v_mad_mixhi_f16_f16lo_f16lo_
}
; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext:
-; GFX9: v_mov_b32_e32 v3, 0
-; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2
-; GFX9-NEXT: v_mov_b32_e32 v0, v3
+; GFX9: s_waitcnt
+; GFX9-NEXT: v_mad_mixlo_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1]
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_setpc_b64
define i32 @v_mad_mixhi_f16_f16lo_f16lo_f16lo_intpack_sext(half %src0, half %src1, half %src2) #0 {
%src0.ext = fpext half %src0 to float
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