[llvm] r345532 - Relax fast register allocator related test cases; NFC
Matthias Braun via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 29 13:10:43 PDT 2018
Author: matze
Date: Mon Oct 29 13:10:42 2018
New Revision: 345532
URL: http://llvm.org/viewvc/llvm-project?rev=345532&view=rev
Log:
Relax fast register allocator related test cases; NFC
- Relex hard coded registers and stack frame sizes
- Some test cleanups
- Change phi-dbg.ll to match on mir output after phi elimination instead
of going through the whole codegen pipeline.
This is in preparation for https://reviews.llvm.org/D52010
I'm committing all the test changes upfront that work before and after
independently.
Modified:
llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-ret.ll
llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll
llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll
llvm/trunk/test/CodeGen/AArch64/fast-isel-atomic.ll
llvm/trunk/test/CodeGen/AArch64/fast-isel-branch-cond-mask.ll
llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll
llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
llvm/trunk/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-align.ll
llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
llvm/trunk/test/CodeGen/ARM/fast-isel.ll
llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
llvm/trunk/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll
llvm/trunk/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
llvm/trunk/test/CodeGen/Mips/Fast-ISel/logopm.ll
llvm/trunk/test/CodeGen/PowerPC/pr26180.ll
llvm/trunk/test/CodeGen/PowerPC/tls.ll
llvm/trunk/test/CodeGen/PowerPC/vsx-spill.ll
llvm/trunk/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
llvm/trunk/test/CodeGen/SystemZ/rosbg-02.ll
llvm/trunk/test/CodeGen/X86/epilogue-cfi-no-fp.ll
llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll
llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll
llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll
llvm/trunk/test/CodeGen/X86/fold-sext-trunc.ll
llvm/trunk/test/CodeGen/X86/pr28489.ll
llvm/trunk/test/CodeGen/X86/pr30813.ll
llvm/trunk/test/CodeGen/X86/shift-i256.ll
llvm/trunk/test/CodeGen/X86/switch.ll
llvm/trunk/test/CodeGen/X86/win32_sret.ll
llvm/trunk/test/CodeGen/XCore/dwarf_debug.ll
llvm/trunk/test/DebugInfo/X86/parameters.ll
llvm/trunk/test/DebugInfo/X86/pieces-1.ll
llvm/trunk/test/DebugInfo/X86/sdag-split-arg.ll
llvm/trunk/test/DebugInfo/X86/vla.ll
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-abi.ll Mon Oct 29 13:10:42 2018
@@ -128,7 +128,7 @@ entry:
; CHECK-LABEL: test3
; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
; FAST-LABEL: test3
-; FAST: sub sp, sp, #48
+; FAST: sub sp, sp, #{{[0-9]+}}
; FAST: mov x[[ADDR:[0-9]+]], sp
; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]
%0 = load <2 x i32>, <2 x i32>* %in, align 8
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-icmp.ll Mon Oct 29 13:10:42 2018
@@ -4,7 +4,8 @@ define i32 @icmp_eq_imm(i32 %a) nounwind
entry:
; CHECK-LABEL: icmp_eq_imm
; CHECK: cmp w0, #31
-; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp eq i32 %a, 31
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -14,7 +15,8 @@ define i32 @icmp_eq_neg_imm(i32 %a) noun
entry:
; CHECK-LABEL: icmp_eq_neg_imm
; CHECK: cmn w0, #7
-; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp eq i32 %a, -7
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -24,7 +26,8 @@ define i32 @icmp_eq_i32(i32 %a, i32 %b)
entry:
; CHECK-LABEL: icmp_eq_i32
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -34,7 +37,8 @@ define i32 @icmp_ne(i32 %a, i32 %b) noun
entry:
; CHECK-LABEL: icmp_ne
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, ne
+; CHECK-NEXT: cset [[REG:w[0-9]+]], ne
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -64,7 +68,8 @@ define i32 @icmp_ugt(i32 %a, i32 %b) nou
entry:
; CHECK-LABEL: icmp_ugt
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, hi
+; CHECK-NEXT: cset [[REG:w[0-9]+]], hi
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -74,7 +79,8 @@ define i32 @icmp_uge(i32 %a, i32 %b) nou
entry:
; CHECK-LABEL: icmp_uge
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, hs
+; CHECK-NEXT: cset [[REG:w[0-9]+]], hs
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -84,7 +90,8 @@ define i32 @icmp_ult(i32 %a, i32 %b) nou
entry:
; CHECK-LABEL: icmp_ult
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, lo
+; CHECK-NEXT: cset [[REG:w[0-9]+]], lo
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -94,7 +101,8 @@ define i32 @icmp_ule(i32 %a, i32 %b) nou
entry:
; CHECK-LABEL: icmp_ule
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, ls
+; CHECK-NEXT: cset [[REG:w[0-9]+]], ls
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp ule i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -104,7 +112,8 @@ define i32 @icmp_sgt(i32 %a, i32 %b) nou
entry:
; CHECK-LABEL: icmp_sgt
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: cset [[REG:w[0-9]+]], gt
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -114,7 +123,8 @@ define i32 @icmp_sge(i32 %a, i32 %b) nou
entry:
; CHECK-LABEL: icmp_sge
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, ge
+; CHECK-NEXT: cset [[REG:w[0-9]+]], ge
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -124,7 +134,8 @@ define i32 @icmp_slt(i32 %a, i32 %b) nou
entry:
; CHECK-LABEL: icmp_slt
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, lt
+; CHECK-NEXT: cset [[REG:w[0-9]+]], lt
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -134,7 +145,8 @@ define i32 @icmp_sle(i32 %a, i32 %b) nou
entry:
; CHECK-LABEL: icmp_sle
; CHECK: cmp w0, w1
-; CHECK-NEXT: cset w0, le
+; CHECK-NEXT: cset [[REG:w[0-9]+]], le
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -144,7 +156,8 @@ define i32 @icmp_i64(i64 %a, i64 %b) nou
entry:
; CHECK-LABEL: icmp_i64
; CHECK: cmp x0, x1
-; CHECK-NEXT: cset w{{[0-9]+}}, le
+; CHECK-NEXT: cset [[REG:w[0-9]+]], le
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@@ -153,9 +166,10 @@ entry:
define zeroext i1 @icmp_eq_i16(i16 %a, i16 %b) nounwind ssp {
entry:
; CHECK-LABEL: icmp_eq_i16
-; CHECK: sxth w0, w0
-; CHECK: cmp w0, w1, sxth
-; CHECK-NEXT: cset w0, eq
+; CHECK: sxth [[REG0:w[0-9]+]], w0
+; CHECK: cmp [[REG0]], w1, sxth
+; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp eq i16 %a, %b
ret i1 %cmp
}
@@ -163,9 +177,10 @@ entry:
define zeroext i1 @icmp_eq_i8(i8 %a, i8 %b) nounwind ssp {
entry:
; CHECK-LABEL: icmp_eq_i8
-; CHECK: sxtb w0, w0
-; CHECK-NEXT: cmp w0, w1, sxtb
-; CHECK-NEXT: cset w0, eq
+; CHECK: sxtb [[REG0:w[0-9]+]], w0
+; CHECK-NEXT: cmp [[REG0]], w1, sxtb
+; CHECK-NEXT: cset [[REG:w[0-9]+]], eq
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp eq i8 %a, %b
ret i1 %cmp
}
@@ -173,9 +188,10 @@ entry:
define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind {
entry:
; CHECK-LABEL: icmp_i16_unsigned
-; CHECK: uxth w0, w0
-; CHECK-NEXT: cmp w0, w1, uxth
-; CHECK-NEXT: cset w0, lo
+; CHECK: uxth [[REG0:w[0-9]+]], w0
+; CHECK-NEXT: cmp [[REG0]], w1, uxth
+; CHECK-NEXT: cset [[REG:w[0-9]+]], lo
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp ult i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@@ -184,9 +200,10 @@ entry:
define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind {
entry:
; CHECK-LABEL: icmp_i8_signed
-; CHECK: sxtb w0, w0
-; CHECK-NEXT: cmp w0, w1, sxtb
-; CHECK-NEXT: cset w0, gt
+; CHECK: sxtb [[REG0:w[0-9]+]], w0
+; CHECK-NEXT: cmp [[REG0]], w1, sxtb
+; CHECK-NEXT: cset [[REG:w[0-9]+]], gt
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp sgt i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@@ -198,7 +215,8 @@ entry:
; CHECK: sbfx [[REG1:w[0-9]+]], w0, #0, #1
; CHECK-NEXT: sbfx [[REG2:w[0-9]+]], w1, #0, #1
; CHECK-NEXT: cmp [[REG1]], [[REG2]]
-; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: cset [[REG:w[0-9]+]], gt
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp sgt i1 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@@ -207,10 +225,10 @@ entry:
define i32 @icmp_i16_signed_const(i16 %a) nounwind {
entry:
; CHECK-LABEL: icmp_i16_signed_const
-; CHECK: sxth w0, w0
-; CHECK-NEXT: cmn w0, #233
-; CHECK-NEXT: cset w0, lt
-; CHECK-NEXT: and w0, w0, #0x1
+; CHECK: sxth [[REG0:w[0-9]+]], w0
+; CHECK-NEXT: cmn [[REG0]], #233
+; CHECK-NEXT: cset [[REG:w[0-9]+]], lt
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp slt i16 %a, -233
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@@ -219,10 +237,10 @@ entry:
define i32 @icmp_i8_signed_const(i8 %a) nounwind {
entry:
; CHECK-LABEL: icmp_i8_signed_const
-; CHECK: sxtb w0, w0
-; CHECK-NEXT: cmp w0, #124
-; CHECK-NEXT: cset w0, gt
-; CHECK-NEXT: and w0, w0, #0x1
+; CHECK: sxtb [[REG0:w[0-9]+]], w0
+; CHECK-NEXT: cmp [[REG0]], #124
+; CHECK-NEXT: cset [[REG:w[0-9]+]], gt
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp sgt i8 %a, 124
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@@ -231,10 +249,10 @@ entry:
define i32 @icmp_i1_unsigned_const(i1 %a) nounwind {
entry:
; CHECK-LABEL: icmp_i1_unsigned_const
-; CHECK: and w0, w0, #0x1
-; CHECK-NEXT: cmp w0, #0
-; CHECK-NEXT: cset w0, lo
-; CHECK-NEXT: and w0, w0, #0x1
+; CHECK: and [[REG0:w[0-9]+]], w0, #0x1
+; CHECK-NEXT: cmp [[REG0]], #0
+; CHECK-NEXT: cset [[REG:w[0-9]+]], lo
+; CHECK-NEXT: and w0, [[REG]], #0x1
%cmp = icmp ult i1 %a, 0
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll Mon Oct 29 13:10:42 2018
@@ -7,8 +7,8 @@ define void @t1() {
; ARM64-LABEL: t1
; ARM64: adrp x8, _message at PAGE
; ARM64: add x0, x8, _message at PAGEOFF
-; ARM64: mov w9, wzr
-; ARM64: uxtb w1, w9
+; ARM64: mov [[REG:w[0-9]+]], wzr
+; ARM64: uxtb w1, [[REG]]
; ARM64: mov x2, #80
; ARM64: bl _memset
call void @llvm.memset.p0i8.i64(i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i1 false)
@@ -48,15 +48,15 @@ declare void @llvm.memmove.p0i8.p0i8.i64
define void @t4() {
; ARM64-LABEL: t4
; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldr x10, [x9]
-; ARM64: str x10, [x8]
-; ARM64: ldr x10, [x9, #8]
-; ARM64: str x10, [x8, #8]
-; ARM64: ldrb w11, [x9, #16]
-; ARM64: strb w11, [x8, #16]
+; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp at GOTPAGEOFF]
+; ARM64: adrp [[REG1:x[0-9]+]], _message at PAGE
+; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message at PAGEOFF
+; ARM64: ldr x10, {{\[}}[[REG2]]{{\]}}
+; ARM64: str x10, {{\[}}[[REG0]]{{\]}}
+; ARM64: ldr x10, {{\[}}[[REG2]], #8]
+; ARM64: str x10, {{\[}}[[REG0]], #8]
+; ARM64: ldrb [[REG3:w[0-9]+]], {{\[}}[[REG2]], #16]
+; ARM64: strb [[REG3]], {{\[}}[[REG0]], #16]
; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 16 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i1 false)
ret void
@@ -65,15 +65,15 @@ define void @t4() {
define void @t5() {
; ARM64-LABEL: t5
; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldr x10, [x9]
-; ARM64: str x10, [x8]
-; ARM64: ldr x10, [x9, #8]
-; ARM64: str x10, [x8, #8]
-; ARM64: ldrb w11, [x9, #16]
-; ARM64: strb w11, [x8, #16]
+; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp at GOTPAGEOFF]
+; ARM64: adrp [[REG3:x[0-9]+]], _message at PAGE
+; ARM64: add [[REG1:x[0-9]+]], [[REG3]], _message at PAGEOFF
+; ARM64: ldr x10, {{\[}}[[REG1]]]
+; ARM64: str x10, {{\[}}[[REG0]]]
+; ARM64: ldr x10, {{\[}}[[REG1]], #8]
+; ARM64: str x10, {{\[}}[[REG0]], #8]
+; ARM64: ldrb [[REG4:w[0-9]+]], {{\[}}[[REG1]], #16]
+; ARM64: strb [[REG4]], {{\[}}[[REG0]], #16]
; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 8 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 17, i1 false)
ret void
@@ -82,15 +82,15 @@ define void @t5() {
define void @t6() {
; ARM64-LABEL: t6
; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldr w10, [x9]
-; ARM64: str w10, [x8]
-; ARM64: ldr w10, [x9, #4]
-; ARM64: str w10, [x8, #4]
-; ARM64: ldrb w10, [x9, #8]
-; ARM64: strb w10, [x8, #8]
+; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp at GOTPAGEOFF]
+; ARM64: adrp [[REG1:x[0-9]+]], _message at PAGE
+; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message at PAGEOFF
+; ARM64: ldr w10, {{\[}}[[REG2]]]
+; ARM64: str w10, {{\[}}[[REG0]]]
+; ARM64: ldr w10, {{\[}}[[REG2]], #4]
+; ARM64: str w10, {{\[}}[[REG0]], #4]
+; ARM64: ldrb [[REG3:w[0-9]+]], {{\[}}[[REG2]], #8]
+; ARM64: strb [[REG3]], {{\[}}[[REG0]], #8]
; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 4 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 9, i1 false)
ret void
@@ -99,17 +99,17 @@ define void @t6() {
define void @t7() {
; ARM64-LABEL: t7
; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldrh w10, [x9]
-; ARM64: strh w10, [x8]
-; ARM64: ldrh w10, [x9, #2]
-; ARM64: strh w10, [x8, #2]
-; ARM64: ldrh w10, [x9, #4]
-; ARM64: strh w10, [x8, #4]
-; ARM64: ldrb w10, [x9, #6]
-; ARM64: strb w10, [x8, #6]
+; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp at GOTPAGEOFF]
+; ARM64: adrp [[REG1:x[0-9]+]], _message at PAGE
+; ARM64: add [[REG2:x[0-9]+]], [[REG1]], _message at PAGEOFF
+; ARM64: ldrh w10, {{\[}}[[REG2]]]
+; ARM64: strh w10, {{\[}}[[REG0]]]
+; ARM64: ldrh w10, {{\[}}[[REG2]], #2]
+; ARM64: strh w10, {{\[}}[[REG0]], #2]
+; ARM64: ldrh w10, {{\[}}[[REG2]], #4]
+; ARM64: strh w10, {{\[}}[[REG0]], #4]
+; ARM64: ldrb [[REG3:w[0-9]+]], {{\[}}[[REG2]], #6]
+; ARM64: strb [[REG3]], {{\[}}[[REG0]], #6]
; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 2 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 2 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 7, i1 false)
ret void
@@ -118,17 +118,17 @@ define void @t7() {
define void @t8() {
; ARM64-LABEL: t8
; ARM64: adrp x8, _temp at GOTPAGE
-; ARM64: ldr x8, [x8, _temp at GOTPAGEOFF]
-; ARM64: adrp x9, _message at PAGE
-; ARM64: add x9, x9, _message at PAGEOFF
-; ARM64: ldrb w10, [x9]
-; ARM64: strb w10, [x8]
-; ARM64: ldrb w10, [x9, #1]
-; ARM64: strb w10, [x8, #1]
-; ARM64: ldrb w10, [x9, #2]
-; ARM64: strb w10, [x8, #2]
-; ARM64: ldrb w10, [x9, #3]
-; ARM64: strb w10, [x8, #3]
+; ARM64: ldr [[REG0:x[0-9]+]], [x8, _temp at GOTPAGEOFF]
+; ARM64: adrp [[REG1:x[0-9]+]], _message at PAGE
+; ARM64: add [[REG2:x[0-9]+]], [[REG1:x[0-9]+]], _message at PAGEOFF
+; ARM64: ldrb w10, {{\[}}[[REG2]]]
+; ARM64: strb w10, {{\[}}[[REG0]]]
+; ARM64: ldrb w10, {{\[}}[[REG2]], #1]
+; ARM64: strb w10, {{\[}}[[REG0]], #1]
+; ARM64: ldrb w10, {{\[}}[[REG2]], #2]
+; ARM64: strb w10, {{\[}}[[REG0]], #2]
+; ARM64: ldrb [[REG3:w[0-9]+]], {{\[}}[[REG2]], #3]
+; ARM64: strb [[REG3]], {{\[}}[[REG0]], #3]
; ARM64: ret
call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 1 getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* align 1 getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 4, i1 false)
ret void
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-ret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-ret.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-ret.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel-ret.ll Mon Oct 29 13:10:42 2018
@@ -35,7 +35,7 @@ entry:
define signext i16 @ret_i16(i16 signext %a) nounwind {
entry:
; CHECK: @ret_i16
-; CHECK: sxth w0, w0
+; CHECK: sxth w0, {{w[0-9]+}}
%a.addr = alloca i16, align 1
store i16 %a, i16* %a.addr, align 1
%0 = load i16, i16* %a.addr, align 1
@@ -45,7 +45,7 @@ entry:
define signext i8 @ret_i8(i8 signext %a) nounwind {
entry:
; CHECK: @ret_i8
-; CHECK: sxtb w0, w0
+; CHECK: sxtb w0, {{w[0-9]+}}
%a.addr = alloca i8, align 1
store i8 %a, i8* %a.addr, align 1
%0 = load i8, i8* %a.addr, align 1
@@ -55,7 +55,8 @@ entry:
define signext i1 @ret_i1(i1 signext %a) nounwind {
entry:
; CHECK: @ret_i1
-; CHECK: and w0, w0, #0x1
+; CHECK: and [[REG:w[0-9]+]], {{w[0-9]+}}, #0x1
+; CHECK: sbfx w0, [[REG]], #0, #1
%a.addr = alloca i1, align 1
store i1 %a, i1* %a.addr, align 1
%0 = load i1, i1* %a.addr, align 1
Modified: llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/arm64-fast-isel.ll Mon Oct 29 13:10:42 2018
@@ -30,11 +30,11 @@ define void @t1(i64 %a) nounwind {
define zeroext i1 @i1(i1 %a) nounwind {
entry:
; CHECK: @i1
-; CHECK: and w0, w0, #0x1
-; CHECK: strb w0, [sp, #15]
-; CHECK: ldrb w0, [sp, #15]
-; CHECK: and w0, w0, #0x1
-; CHECK: and w0, w0, #0x1
+; CHECK: and [[REG:w[0-9]+]], w0, #0x1
+; CHECK: strb [[REG]], [sp, #15]
+; CHECK: ldrb [[REG1:w[0-9]+]], [sp, #15]
+; CHECK: and [[REG2:w[0-9]+]], [[REG1]], #0x1
+; CHECK: and w0, [[REG2]], #0x1
; CHECK: add sp, sp, #16
; CHECK: ret
%a.addr = alloca i1, align 1
Modified: llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-address-extends.ll Mon Oct 29 13:10:42 2018
@@ -6,8 +6,10 @@ target triple = "arm64-apple-ios8.0.0"
; This test was trying to fold the sext %tmp142 in to the address arithmetic in %sunkaddr1.
; This was incorrect as %.mux isn't available in the last bb.
-; CHECK: sxtw [[REG:x[0-9]+]]
-; CHECK: strh wzr, {{\[}}[[REG]], {{.*}}, lsl #1]
+; CHECK: sxtw [[REG0:x[0-9]+]]
+; CHECK: str [[REG0]], [sp, [[OFFSET:#[0-9]+]]]
+; CHECK: ldr [[REG1:x[0-9]+]], [sp, [[OFFSET]]]
+; CHECK: strh wzr, [{{.*}}, [[REG1]], lsl #1]
; Function Attrs: nounwind optsize ssp
define void @EdgeLoop(i32 %dir, i32 %edge, i32 %width, i16* %tmp89, i32 %tmp136, i16 %tmp144) #0 {
Modified: llvm/trunk/test/CodeGen/AArch64/fast-isel-atomic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-atomic.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-atomic.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-atomic.ll Mon Oct 29 13:10:42 2018
@@ -91,8 +91,8 @@ define void @atomic_store_release_8(i8*
; CHECK-LABEL: atomic_store_release_8_off:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: add x0, x0, #1
-; CHECK-NEXT: stlrb w1, [x0]
+; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #1
+; CHECK-NEXT: stlrb w1, {{\[}}[[REG0]]]
; CHECK-NEXT: ret
define void @atomic_store_release_8_off(i8* %p, i8 %val) #0 {
%tmp0 = getelementptr i8, i8* %p, i32 1
@@ -111,8 +111,8 @@ define void @atomic_store_release_16(i16
; CHECK-LABEL: atomic_store_release_16_off:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: add x0, x0, #2
-; CHECK-NEXT: stlrh w1, [x0]
+; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #2
+; CHECK-NEXT: stlrh w1, {{\[}}[[REG0]]]
; CHECK-NEXT: ret
define void @atomic_store_release_16_off(i16* %p, i16 %val) #0 {
%tmp0 = getelementptr i16, i16* %p, i32 1
@@ -131,8 +131,8 @@ define void @atomic_store_release_32(i32
; CHECK-LABEL: atomic_store_release_32_off:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: add x0, x0, #4
-; CHECK-NEXT: stlr w1, [x0]
+; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #4
+; CHECK-NEXT: stlr w1, {{\[}}[[REG0]]]
; CHECK-NEXT: ret
define void @atomic_store_release_32_off(i32* %p, i32 %val) #0 {
%tmp0 = getelementptr i32, i32* %p, i32 1
@@ -151,8 +151,8 @@ define void @atomic_store_release_64(i64
; CHECK-LABEL: atomic_store_release_64_off:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: add x0, x0, #8
-; CHECK-NEXT: stlr x1, [x0]
+; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #8
+; CHECK-NEXT: stlr x1, {{\[}}[[REG0]]]
; CHECK-NEXT: ret
define void @atomic_store_release_64_off(i64* %p, i64 %val) #0 {
%tmp0 = getelementptr i64, i64* %p, i32 1
@@ -172,8 +172,8 @@ define void @atomic_store_seq_cst_8(i8*
; CHECK-LABEL: atomic_store_seq_cst_8_off:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: add x0, x0, #1
-; CHECK-NEXT: stlrb w1, [x0]
+; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #1
+; CHECK-NEXT: stlrb w1, {{\[}}[[REG0]]]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_8_off(i8* %p, i8 %val) #0 {
%tmp0 = getelementptr i8, i8* %p, i32 1
@@ -192,8 +192,8 @@ define void @atomic_store_seq_cst_16(i16
; CHECK-LABEL: atomic_store_seq_cst_16_off:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: add x0, x0, #2
-; CHECK-NEXT: stlrh w1, [x0]
+; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #2
+; CHECK-NEXT: stlrh w1, {{\[}}[[REG0]]]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_16_off(i16* %p, i16 %val) #0 {
%tmp0 = getelementptr i16, i16* %p, i32 1
@@ -212,8 +212,8 @@ define void @atomic_store_seq_cst_32(i32
; CHECK-LABEL: atomic_store_seq_cst_32_off:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: add x0, x0, #4
-; CHECK-NEXT: stlr w1, [x0]
+; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #4
+; CHECK-NEXT: stlr w1, {{\[}}[[REG0]]]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_32_off(i32* %p, i32 %val) #0 {
%tmp0 = getelementptr i32, i32* %p, i32 1
@@ -232,8 +232,8 @@ define void @atomic_store_seq_cst_64(i64
; CHECK-LABEL: atomic_store_seq_cst_64_off:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: add x0, x0, #8
-; CHECK-NEXT: stlr x1, [x0]
+; CHECK-NEXT: add [[REG0:x[0-9]+]], x0, #8
+; CHECK-NEXT: stlr x1, {{\[}}[[REG0]]]
; CHECK-NEXT: ret
define void @atomic_store_seq_cst_64_off(i64* %p, i64 %val) #0 {
%tmp0 = getelementptr i64, i64* %p, i32 1
Modified: llvm/trunk/test/CodeGen/AArch64/fast-isel-branch-cond-mask.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-branch-cond-mask.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-branch-cond-mask.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-branch-cond-mask.ll Mon Oct 29 13:10:42 2018
@@ -2,9 +2,9 @@
define void @test(i64 %a, i64 %b, i2* %c) {
; CHECK-LABEL: test
-; CHECK: and [[REG1:w[0-9]+]], w8, #0x3
+; CHECK: and [[REG1:w[0-9]+]], {{w[0-9]+}}, #0x3
; CHECK-NEXT: strb [[REG1]], {{\[}}x2{{\]}}
-; CHECK-NEXT: tbz w9, #0,
+; CHECK-NEXT: tbz {{w[0-9]+}}, #0,
%1 = trunc i64 %a to i2
%2 = trunc i64 %b to i1
; Force fast-isel to fall back to SDAG.
Modified: llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/phi-dbg.ll Mon Oct 29 13:10:42 2018
@@ -1,4 +1,4 @@
-; RUN: llc -O0 %s -mtriple=aarch64 -o - | FileCheck %s
+; RUN: llc -O0 %s -mtriple=aarch64 -stop-after=phi-node-elimination -o - | FileCheck %s
; Test that a DEBUG_VALUE node is create for variable c after the phi has been
; converted to a ldr. The DEBUG_VALUE must be *after* the ldr and not before it.
@@ -15,25 +15,34 @@
; }
;
; Function Attrs: nounwind
-define i32 @func(i32) #0 !dbg !8 {
- call void @llvm.dbg.value(metadata i32 %0, i64 0, metadata !12, metadata !13), !dbg !14
+; CHECK: !14 = !DILocalVariable(name: "c"
+; CHECK-LABEL: name: func
+define i32 @func(i32 %a0) #0 !dbg !8 {
+entry:
+ call void @llvm.dbg.value(metadata i32 %a0, i64 0, metadata !12, metadata !13), !dbg !14
call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !15, metadata !13), !dbg !16
- %2 = icmp slt i32 %0, 0, !dbg !17
- br i1 %2, label %3, label %4, !dbg !19
+ %v2 = icmp slt i32 %a0, 0, !dbg !17
+ br i1 %v2, label %bb2, label %bb3, !dbg !19
-; <label>:3: ; preds = %1
+bb2:
call void @llvm.dbg.value(metadata i32 12, i64 0, metadata !15, metadata !13), !dbg !16
- br label %4, !dbg !20
+ br label %bb3, !dbg !20
-; <label>:4: ; preds = %3, %1
- %.0 = phi i32 [ 12, %3 ], [ 1, %1 ]
-; CHECK: ldr w[[REG:[0-9]+]], [sp, #8]
-; CHECK-NEXT: .Ltmp
+; CHECK: bb.2.bb2:
+; CHECK: [[REG0:%[0-9]+]]:gpr32 = MOVi32imm 12
+; CHECK: [[PHIREG:%[0-9]+]]:gpr32 = COPY [[REG0]]
+
+bb3:
+; CHECK: bb.3.bb3:
+; CHECK: [[PHIDEST:%[0-9]+]]:gpr32 = COPY [[PHIREG]]
+; CHECK-NEXT: DBG_VALUE debug-use [[PHIDEST]]
+ %.0 = phi i32 [ 12, %bb2 ], [ 1, %entry ]
call void @llvm.dbg.value(metadata i32 %.0, i64 0, metadata !15, metadata !13), !dbg !16
-; CHECK-NEXT: //DEBUG_VALUE: func:c <- $w[[REG]]
- %5 = add nsw i32 %.0, %0, !dbg !22
- call void @llvm.dbg.value(metadata i32 %5, i64 0, metadata !15, metadata !13), !dbg !16
- ret i32 %5, !dbg !23
+; CHECK: [[ADD:%[0-9]+]]:gpr32 = nsw ADDWrr [[PHIDEST]]
+; CHECK-NEXT: DBG_VALUE debug-use [[ADD]]
+ %v5 = add nsw i32 %.0, %a0, !dbg !22
+ call void @llvm.dbg.value(metadata i32 %v5, i64 0, metadata !15, metadata !13), !dbg !16
+ ret i32 %v5, !dbg !23
}
; Function Attrs: nounwind readnone
Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll Mon Oct 29 13:10:42 2018
@@ -19,7 +19,7 @@ define amdgpu_kernel void @dpp_test(i32
; VI-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0
; VI-NEXT: s_nop 0
; VI-NEXT: s_nop 0
-; VI-NEXT: v_mov_b32_dpp v2, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
+; VI-NEXT: v_mov_b32_dpp {{v[0-9]+}}, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
@0 = internal unnamed_addr addrspace(3) global [448 x i32] undef, align 4
define weak_odr amdgpu_kernel void @dpp_test1(i32* %arg) local_unnamed_addr {
bb:
Modified: llvm/trunk/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/spill-wide-sgpr.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/spill-wide-sgpr.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/spill-wide-sgpr.ll Mon Oct 29 13:10:42 2018
@@ -45,11 +45,11 @@ ret:
; ALL-LABEL: {{^}}spill_sgpr_x4:
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
-; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[12:15], m0 ; 16-byte Folded Spill
+; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS:[0-9]+:[0-9]+]]{{\]}}, m0 ; 16-byte Folded Spill
; SMEM: s_cbranch_scc1
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
-; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[12:15], m0 ; 16-byte Folded Reload
+; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
; SMEM: s_dcache_wb
; SMEM: s_endpgm
@@ -94,15 +94,15 @@ ret:
; ALL-LABEL: {{^}}spill_sgpr_x8:
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
-; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[16:19], m0 ; 16-byte Folded Spill
+; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS:[0-9]+:[0-9]+]]{{\]}}, m0 ; 16-byte Folded Spill
; SMEM: s_add_u32 m0, s3, 0x110{{$}}
-; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[16:19], m0 ; 16-byte Folded Spill
+; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Spill
; SMEM: s_cbranch_scc1
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
-; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[16:19], m0 ; 16-byte Folded Reload
+; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
; SMEM: s_add_u32 m0, s3, 0x110{{$}}
-; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s[16:19], m0 ; 16-byte Folded Reload
+; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
; SMEM: s_dcache_wb
; SMEM: s_endpgm
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-align.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-align.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-align.ll Mon Oct 29 13:10:42 2018
@@ -26,12 +26,12 @@
define void @unaligned_store(float %x, float %y) nounwind {
entry:
; ARM: @unaligned_store
-; ARM: vmov r1, s0
-; ARM: str r1, [r0]
+; ARM: vmov [[REG:r[0-9]+]], s0
+; ARM: str [[REG]], [{{r[0-9]+}}]
; THUMB: @unaligned_store
-; THUMB: vmov r1, s0
-; THUMB: str r1, [r0]
+; THUMB: vmov [[REG:r[0-9]+]], s0
+; THUMB: str [[REG]], [{{r[0-9]+}}]
%add = fadd float %x, %y
%0 = load %struct.anon*, %struct.anon** @a, align 4
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll Mon Oct 29 13:10:42 2018
@@ -82,7 +82,8 @@ entry:
; ARM: t9
%add.ptr = getelementptr inbounds i16, i16* %a, i64 -8
store i16 0, i16* %add.ptr, align 2
-; ARM: strh r1, [r0, #-16]
+; ARM: movw [[REG0:r[0-9]+]], #0
+; ARM: strh [[REG0]], [{{r[0-9]+}}, #-16]
ret void
}
@@ -93,9 +94,10 @@ entry:
; ARM: t10
%add.ptr = getelementptr inbounds i16, i16* %a, i64 -128
store i16 0, i16* %add.ptr, align 2
-; ARM: mvn r{{[1-9]}}, #255
-; ARM: add r0, r0, r{{[1-9]}}
-; ARM: strh r{{[1-9]}}, [r0]
+; ARM: mvn r1, #255
+; ARM: add [[REG0:r[0-9]+]], r0, r1
+; ARM: movw [[REG1:r[0-9]+]], #0
+; ARM: strh [[REG1]], {{\[}}[[REG0]]]
ret void
}
@@ -104,7 +106,8 @@ entry:
; ARM: t11
%add.ptr = getelementptr inbounds i16, i16* %a, i64 8
store i16 0, i16* %add.ptr, align 2
-; ARM: strh r{{[1-9]}}, [r0, #16]
+; ARM: movw [[REG1:r[0-9]+]], #0
+; ARM: strh [[REG1]], [{{r[0-9]+}}, #16]
ret void
}
@@ -115,8 +118,9 @@ entry:
; ARM: t12
%add.ptr = getelementptr inbounds i16, i16* %a, i64 128
store i16 0, i16* %add.ptr, align 2
-; ARM: add r0, r0, #256
-; ARM: strh r{{[1-9]}}, [r0]
+; ARM: add [[REG0:r[0-9]+]], r0, #256
+; ARM: movw [[REG1:r[0-9]+]], #0
+; ARM: strh [[REG1]], {{\[}}[[REG0]]]
ret void
}
Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Mon Oct 29 13:10:42 2018
@@ -149,21 +149,21 @@ define void @test4() {
; THUMB: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
-; THUMB: ldr r0, [r0]
-; THUMB: ldr r1, [r0]
-; THUMB: adds r1, #1
-; THUMB: str r1, [r0]
+; THUMB: ldr [[REG:r[0-9]+]], [r0]
+; THUMB: ldr [[REG1:r[0-9]+]], {{\[}}[[REG]]]
+; THUMB: adds [[REG1]], #1
+; THUMB: str [[REG1]], {{\[}}[[REG]]]
; ARM-MACHO: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}}
-; ARM-MACHO: ldr r0, [r0]
+; ARM-MACHO: ldr [[REG:r[0-9]+]], [r0]
-; ARM-ELF: movw r0, :lower16:test4g
-; ARM-ELF: movt r0, :upper16:test4g
+; ARM-ELF: movw [[REG:r[0-9]+]], :lower16:test4g
+; ARM-ELF: movt [[REG]], :upper16:test4g
-; ARM: ldr r1, [r0]
-; ARM: add r1, r1, #1
-; ARM: str r1, [r0]
+; ARM: ldr [[REG1:r[0-9]+]], {{\[}}[[REG]]]
+; ARM: add [[REG2:r[0-9]+]], [[REG1]], #1
+; ARM: str [[REG2]], {{\[}}[[REG]]]
}
; ARM: @urem_fold
Modified: llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll Mon Oct 29 13:10:42 2018
@@ -1043,7 +1043,7 @@ entry:
; CHECK-SPILL-RELOAD-LABEL: fn1:
; CHECK-SPILL-RELOAD: vstr.16 s0, [sp, #{{.}}] @ 2-byte Spill
-; CHECK-SPILL-RELOAD-NEXT: bl fn2
+; CHECK-SPILL-RELOAD: bl fn2
; CHECK-SPILL-RELOAD-NEXT: vldr.16 s0, [sp, #{{.}}] @ 2-byte Reload
}
Modified: llvm/trunk/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/bricmpi1.ll Mon Oct 29 13:10:42 2018
@@ -109,11 +109,11 @@ end:
define void @testsgt(i32, i32) {
; CHECK-LABEL: testsgt:
; CHECK: andi $[[REG0:[0-9]+]], $4, 1
-; CHECK: negu $[[REG0]], $[[REG0]]
+; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]]
; CHECK: andi $[[REG1:[0-9]+]], $5, 1
-; CHECK: negu $[[REG1]], $[[REG1]]
-; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
-; CHECK: bnez $[[REG2]],
+; CHECK: negu $[[REG3:[0-9]+]], $[[REG1]]
+; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]]
+; CHECK: bnez $[[REG4]],
%3 = trunc i32 %0 to i1
%4 = trunc i32 %1 to i1
%5 = icmp sgt i1 %3, %4
@@ -169,11 +169,11 @@ end:
define void @testsle(i32, i32) {
; CHECK-LABEL: testsle:
; CHECK: andi $[[REG0:[0-9]+]], $4, 1
-; CHECK: negu $[[REG0]], $[[REG0]]
+; CHECK: negu $[[REG2:[0-9]+]], $[[REG0]]
; CHECK: andi $[[REG1:[0-9]+]], $5, 1
-; CHECK: negu $[[REG1]], $[[REG1]]
-; CHECK: slt $[[REG2:[0-9]+]], $[[REG1]], $[[REG0]]
-; CHECK: beqz $[[REG2]],
+; CHECK: negu $[[REG3:[0-9]+]], $[[REG1]]
+; CHECK: slt $[[REG4:[0-9]+]], $[[REG3]], $[[REG2]]
+; CHECK: beqz $[[REG4]],
%3 = trunc i32 %0 to i1
%4 = trunc i32 %1 to i1
%5 = icmp sle i1 %3, %4
Modified: llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll Mon Oct 29 13:10:42 2018
@@ -180,7 +180,7 @@ define void @cxcccc() {
; 32R1: sra $7, $[[R]], 24
; 32R2: seb $7, $[[R]]
- ; ALL: lw $25, %got(xcccc)($2)
+ ; ALL: lw $25, %got(xcccc)(${{[0-9]+}})
; ALL: jalr $25
; ALL: jr $ra
call void @xcccc(i8 88, i8 44, i8 11, i8 33)
@@ -209,7 +209,7 @@ define void @cxhhhh() {
; 32R1: sra $7, $[[R]], 16
; 32R2: seh $7, $[[R]]
- ; ALL: lw $25, %got(xhhhh)($2)
+ ; ALL: lw $25, %got(xhhhh)(${{[0-9]+}})
; ALL: jalr $25
; ALL: jr $ra
Modified: llvm/trunk/test/CodeGen/Mips/Fast-ISel/fastalloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/fastalloca.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/fastalloca.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/fastalloca.ll Mon Oct 29 13:10:42 2018
@@ -22,8 +22,8 @@ entry:
%2 = load i32, i32* %x2, align 4
store i32 %2, i32* @i, align 4
%3 = load i32, i32* %retval
-; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
-; CHECK-DAG: addiu $[[A_ADDR:[0-9]+]], $sp, 8
+; CHECK: lw $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
+; CHECK: addiu $[[A_ADDR:[0-9]+]], $sp, 8
; CHECK-DAG: sw $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp)
; CHECK-DAG: lw $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp)
; CHECK-DAG: lw $[[A_X:[0-9]+]], 0($[[A_ADDR2]])
Modified: llvm/trunk/test/CodeGen/Mips/Fast-ISel/logopm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/logopm.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/logopm.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/logopm.ll Mon Oct 29 13:10:42 2018
@@ -245,7 +245,7 @@ entry:
; CHECK-DAG: lw $[[UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
; CHECK-DAG: lbu $[[UC1:[0-9]+]], 0($[[UC1_ADDR]])
; CHECK-DAG: lbu $[[UC2:[0-9]+]], 0($[[UC2_ADDR]])
-; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC2]], $[[UB1]]
+; CHECK-DAG: and $[[RES:[0-9]+]], $[[UC2]], $[[UC1]]
; CHECK: sb $[[RES]], 0($[[UC_ADDR]])
ret void
}
@@ -430,7 +430,7 @@ entry:
; CHECK-DAG: lw $[[US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
-; CHECK-DAG: and $[[RES:[0-9]+]], $[[US2]], $[[UB1]]
+; CHECK-DAG: and $[[RES:[0-9]+]], $[[US2]], $[[US1]]
; CHECK: sh $[[RES]], 0($[[US_ADDR]])
; CHECK: .end andUs
ret void
Modified: llvm/trunk/test/CodeGen/PowerPC/pr26180.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/pr26180.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/pr26180.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/pr26180.ll Mon Oct 29 13:10:42 2018
@@ -6,9 +6,9 @@ define i32 @bad(double %x) {
ret i32 %1
}
-; CHECK: fctidz 1, 1
-; CHECK: stfd 1, [[OFF:.*]](1)
+; CHECK: fctidz [[REG0:[0-9]+]], 1
+; CHECK: stfd [[REG0]], [[OFF:.*]](1)
; CHECK: lwz {{[0-9]*}}, [[OFF]](1)
-; GENERIC: fctiwuz 1, 1
-; GENERIC: stfd 1, [[OFF:.*]](1)
+; GENERIC: fctiwuz [[REG0:[0-9]+]], 1
+; GENERIC: stfd [[REG0]], [[OFF:.*]](1)
; GENERIC: lwz {{[0-9]*}}, [[OFF]](1)
Modified: llvm/trunk/test/CodeGen/PowerPC/tls.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/tls.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/tls.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/tls.ll Mon Oct 29 13:10:42 2018
@@ -11,12 +11,12 @@ target triple = "powerpc64-unknown-linux
define i32 @localexec() nounwind {
entry:
;OPT0: addis [[REG1:[0-9]+]], 13, a at tprel@ha
-;OPT0-NEXT: addi [[REG1]], [[REG1]], a at tprel@l
-;OPT0-NEXT: li [[REG2:[0-9]+]], 42
-;OPT0: stw [[REG2]], 0([[REG1]])
+;OPT0-NEXT: addi [[REG2:[0-9]+]], [[REG1]], a at tprel@l
+;OPT0-NEXT: li [[REG3:[0-9]+]], 42
+;OPT0: stw [[REG3]], 0([[REG2]])
;OPT1: addis [[REG1:[0-9]+]], 13, a at tprel@ha
-;OPT1-NEXT: li [[REG2:[0-9]+]], 42
-;OPT1: stw [[REG2]], a at tprel@l([[REG1]])
+;OPT1-NEXT: li [[REG3:[0-9]+]], 42
+;OPT1: stw [[REG3]], a at tprel@l([[REG1]])
store i32 42, i32* @a, align 4
ret i32 0
}
Modified: llvm/trunk/test/CodeGen/PowerPC/vsx-spill.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/vsx-spill.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/vsx-spill.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/vsx-spill.ll Mon Oct 29 13:10:42 2018
@@ -60,8 +60,8 @@ entry:
; CHECK-REG: blr
; CHECK-FISL: @foo2
-; CHECK-FISL: xsadddp f1, f1, f1
-; CHECK-FISL: stxsdx f1, r1, r3
+; CHECK-FISL: xsadddp [[REG0:f[0-9]+]], f1, f1
+; CHECK-FISL: stxsdx [[REG0]], r1, r3
; CHECK-FISL: lxsdx f1, r1, r3
; CHECK-FISL: blr
@@ -71,8 +71,8 @@ entry:
; CHECK-P9-REG: blr
; CHECK-P9-FISL: @foo2
-; CHECK-P9-FISL: xsadddp f1, f1, f1
-; CHECK-P9-FISL: stfd f1, -152(r1)
+; CHECK-P9-FISL: xsadddp [[REG0:f[0-9]+]], f1, f1
+; CHECK-P9-FISL: stfd [[REG0]], -152(r1)
; CHECK-P9-FISL: lfd f1, -152(r1)
; CHECK-P9-FISL: blr
Modified: llvm/trunk/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/LeonCASAInstructionUT.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/LeonCASAInstructionUT.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/LeonCASAInstructionUT.ll Mon Oct 29 13:10:42 2018
@@ -19,7 +19,9 @@
; RUN: llc %s -O0 -march=sparc -mcpu=ma2x8x -o - | FileCheck %s
; CHECK-LABEL: casa_test
-; CHECK: casa [%o0] 10, %o3, %o2
+; CHECK-DAG: mov 1, [[R0:%[a-z0-9]+]]
+; CHECK-DAG: mov %g0, [[R1:%[a-z0-9]+]]
+; CHECK: casa [{{%[a-z0-9]+}}] 10, [[R1]], [[R0]]
define void @casa_test(i32* %ptr) {
%pair = cmpxchg i32* %ptr, i32 0, i32 1 monotonic monotonic
%r = extractvalue { i32, i1 } %pair, 0
Modified: llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir (original)
+++ llvm/trunk/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir Mon Oct 29 13:10:42 2018
@@ -13,22 +13,18 @@
name: main
alignment: 2
tracksRegLiveness: true
-registers:
- - { id: 0, class: gr128bit }
- - { id: 1, class: gr64bit }
- - { id: 2, class: addr64bit }
-# CHECK: $r0q = L128
-# CHECK-NEXT: $r0l = COPY renamable $r1l
+# CHECK: $r0l = COPY renamable $r1l
# Although R0L partially redefines R0Q, it must not mark R0Q as kill
# because R1D is still live through that instruction.
# CHECK-NOT: implicit killed $r0q
-# CHECK-NEXT: $r2d = COPY renamable $r1d
+# CHECK-NEXT: {{\$r[0-9]+d}} = COPY renamable $r1d
# CHECK-NEXT: LARL
body: |
bb.0:
+ %0 : gr128bit = IMPLICIT_DEF
%0.subreg_hl32 = COPY %0.subreg_l32
- %1 = COPY %0.subreg_l64
- %2 = LARL @g_167
+ %1 : gr64bit = COPY %0.subreg_l64
+ %2 : addr64bit = LARL @g_167
STC %1.subreg_l32, %2, 8, $noreg
...
Modified: llvm/trunk/test/CodeGen/SystemZ/rosbg-02.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SystemZ/rosbg-02.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SystemZ/rosbg-02.ll (original)
+++ llvm/trunk/test/CodeGen/SystemZ/rosbg-02.ll Mon Oct 29 13:10:42 2018
@@ -18,7 +18,7 @@ define void @main() {
%7 = zext i1 %6 to i32
%8 = load i32, i32* @g_999, align 4
%9 = or i32 %8, %7
-; CHECK: rosbg %r1, %r3, 63, 63, 33
+; CHECK: rosbg {{%r[0-9]+}}, {{%r[0-9]+}}, 63, 63, 33
store i32 %9, i32* @g_999, align 4
ret void
}
Modified: llvm/trunk/test/CodeGen/X86/epilogue-cfi-no-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/epilogue-cfi-no-fp.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/epilogue-cfi-no-fp.ll (original)
+++ llvm/trunk/test/CodeGen/X86/epilogue-cfi-no-fp.ll Mon Oct 29 13:10:42 2018
@@ -1,33 +1,19 @@
; RUN: llc -O0 < %s | FileCheck %s
-
-target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
-target triple = "i686-pc-linux"
+target triple = "i686--"
; Function Attrs: noinline nounwind
define i32 @foo(i32 %i, i32 %j, i32 %k, i32 %l, i32 %m) {
; CHECK-LABEL: foo:
-; CHECK: addl $20, %esp
+; CHECK: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: popl %esi
-; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: popl %edi
-; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: popl %ebx
+; CHECK-NEXT: .cfi_def_cfa_offset 8
+; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
entry:
- %i.addr = alloca i32, align 4
- %j.addr = alloca i32, align 4
- %k.addr = alloca i32, align 4
- %l.addr = alloca i32, align 4
- %m.addr = alloca i32, align 4
- store i32 %i, i32* %i.addr, align 4
- store i32 %j, i32* %j.addr, align 4
- store i32 %k, i32* %k.addr, align 4
- store i32 %l, i32* %l.addr, align 4
- store i32 %m, i32* %m.addr, align 4
+ tail call void asm sideeffect "nop", "~{eax},~{ebx},~{ecx},~{edx},~{esi},~{edi},~{ebp}"()
ret i32 0
}
-
-
-
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Mon Oct 29 13:10:42 2018
@@ -12,7 +12,8 @@ define void @test1(i64*) nounwind ssp {
ret void
; CHECK-LABEL: test1:
; CHECK: callq _f
-; CHECK-NEXT: addq $10, %rax
+; CHECK-NOT: %rax
+; CHECK: addq $10, %rax
}
define void @test2(i64*) nounwind ssp {
@@ -23,7 +24,8 @@ define void @test2(i64*) nounwind ssp {
ret void
; CHECK-LABEL: test2:
; CHECK: callq _f
-; CHECK-NEXT: addq $10, %rdx
+; CHECK-NOT: %rdx
+; CHECK: addq $10, %rdx
}
declare %addovf @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Mon Oct 29 13:10:42 2018
@@ -24,7 +24,7 @@ define i32 @test2(i64 %t3, i32* %t1) nou
%t15 = load i32, i32* %t9 ; <i32> [#uses=1]
ret i32 %t15
; X32-LABEL: test2:
-; X32: movl (%edx,%ecx,4), %e
+; X32: movl ({{%e[a-z]+}},{{%e[a-z]+}},4), %e
; X32: ret
; X64-LABEL: test2:
@@ -81,8 +81,8 @@ define i64 @test5(i8* %A, i32 %I, i64 %B
%v11 = add i64 %B, %v10
ret i64 %v11
; X64-LABEL: test5:
-; X64: movslq %e[[A1]], %rax
-; X64-NEXT: (%r[[A0]],%rax),
+; X64: movslq %e[[A1]], [[R0:%r[a-z]+]]
+; X64-NEXT: (%r[[A0]],[[R0]]),
; X64: ret
}
Modified: llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fast-isel-x86-64.ll Mon Oct 29 13:10:42 2018
@@ -84,7 +84,7 @@ entry:
ret i64 %mul
; CHECK-LABEL: test6:
-; CHECK: shlq $3, %rdi
+; CHECK: shlq $3, {{%r[a-z]+}}
}
define i32 @test7(i32 %x) nounwind ssp {
@@ -92,7 +92,7 @@ entry:
%mul = mul nsw i32 %x, 8
ret i32 %mul
; CHECK-LABEL: test7:
-; CHECK: shll $3, %edi
+; CHECK: shll $3, {{%e[a-z]+}}
}
@@ -103,7 +103,7 @@ entry:
ret i64 %add
; CHECK-LABEL: test8:
-; CHECK: addq $7, %rdi
+; CHECK: addq $7, {{%r[a-z]+}}
}
define i64 @test9(i64 %x) nounwind ssp {
@@ -297,8 +297,10 @@ define void @test23(i8* noalias sret %re
%b = call i8* @foo23()
ret void
; CHECK-LABEL: test23:
+; CHECK: movq %rdi, [[STACK:[0-9]+\(%rsp\)]]
; CHECK: call
-; CHECK: movq %rdi, %rax
+; CHECK: movq [[STACK]], %rdi
+; CHECK: movq %rdi, %rax
; CHECK: ret
}
Modified: llvm/trunk/test/CodeGen/X86/fold-sext-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-sext-trunc.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-sext-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fold-sext-trunc.ll Mon Oct 29 13:10:42 2018
@@ -13,7 +13,7 @@ define void @int322(i32 %foo) !dbg !5 {
entry:
%val = load i64, i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0), !dbg !16
%0 = load i32, i32* getelementptr inbounds (%struct.S1, %struct.S1* @g_10, i32 0, i32 1), align 4, !dbg !17
-; MIR: renamable $rax = MOVSX64rm32 {{.*}}, @g_10 + 4,{{.*}} debug-location !17 :: (dereferenceable load 4 from `i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0)` + 4)
+; MIR: renamable {{\$r[a-z]+}} = MOVSX64rm32 {{.*}}, @g_10 + 4,{{.*}} debug-location !17 :: (dereferenceable load 4 from `i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0)` + 4)
%1 = sext i32 %0 to i64, !dbg !18
%tmp4.i = lshr i64 %val, 32, !dbg !19
%tmp5.i = trunc i64 %tmp4.i to i32, !dbg !20
Modified: llvm/trunk/test/CodeGen/X86/pr28489.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr28489.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr28489.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr28489.ll Mon Oct 29 13:10:42 2018
@@ -3,8 +3,8 @@ declare void @g(i32, i1)
;CHECK-LABEL: f:
;CHECK: cmpxchg8b
-;CHECK: sete %cl
-;CHECK: movzbl %cl
+;CHECK: sete [[REG:%[abcd]l]]
+;CHECK: movzbl [[REG]]
define void @f(i64* %arg, i64 %arg1) {
entry:
%tmp5 = cmpxchg i64* %arg, i64 %arg1, i64 %arg1 seq_cst seq_cst
Modified: llvm/trunk/test/CodeGen/X86/pr30813.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr30813.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr30813.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr30813.ll Mon Oct 29 13:10:42 2018
@@ -1,9 +1,9 @@
; RUN: llc -mtriple=x86_64-linux-gnu -O0 %s -o - | FileCheck %s
; CHECK: patatino:
; CHECK: .cfi_startproc
-; CHECK: movzwl (%rax), %ecx
-; CHECK: movl %ecx, %eax
-; CHECK: movq %rax, (%rdx)
+; CHECK: movzwl (%rax), [[REG0:%e[abcd]x]]
+; CHECK: movl [[REG0]], %e[[REG1C:[abcd]]]x
+; CHECK: movq %r[[REG1C]]x, ({{%r[abcd]x}})
; CHECK: retq
define void @patatino() {
Modified: llvm/trunk/test/CodeGen/X86/shift-i256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shift-i256.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/shift-i256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/shift-i256.ll Mon Oct 29 13:10:42 2018
@@ -15,7 +15,7 @@ define i256 @shift2(i256 %c) nounwind
{
%b = shl i256 1, %c ; %c must not be a constant
; Special case when %c is 0:
- ; CHECK-X64: testb [[REG:%r[0-9]+b]], [[REG]]
+ ; CHECK-X64: testb [[REG:%(bpl|r[0-9]+b)]], {{%(bpl|r[0-9]+b)}}
; CHECK-X64: cmoveq
ret i256 %b
}
Modified: llvm/trunk/test/CodeGen/X86/switch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/switch.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/switch.ll (original)
+++ llvm/trunk/test/CodeGen/X86/switch.ll Mon Oct 29 13:10:42 2018
@@ -318,15 +318,15 @@ return: ret void
; NOOPT-LABEL: optimal_jump_table1
; NOOPT: testl %edi, %edi
; NOOPT: je
-; NOOPT: subl $5, %eax
+; NOOPT: subl $5, [[REG:%e[abcd][xi]]]
; NOOPT: je
-; NOOPT: subl $6, %eax
+; NOOPT: subl $6, [[REG]]
; NOOPT: je
-; NOOPT: subl $12, %eax
+; NOOPT: subl $12, [[REG]]
; NOOPT: je
-; NOOPT: subl $13, %eax
+; NOOPT: subl $13, [[REG]]
; NOOPT: je
-; NOOPT: subl $15, %eax
+; NOOPT: subl $15, [[REG]]
; NOOPT: je
}
Modified: llvm/trunk/test/CodeGen/X86/win32_sret.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win32_sret.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/win32_sret.ll (original)
+++ llvm/trunk/test/CodeGen/X86/win32_sret.ll Mon Oct 29 13:10:42 2018
@@ -16,7 +16,7 @@
define void @sret1(i8* sret %x) nounwind {
entry:
; WIN32-LABEL: _sret1:
-; WIN32: movb $42, (%eax)
+; WIN32: movb $42, ({{%e[abcd]x}})
; WIN32-NOT: popl %eax
; WIN32: {{retl$}}
@@ -36,7 +36,7 @@ entry:
define void @sret2(i8* sret %x, i8 %y) nounwind {
entry:
; WIN32-LABEL: _sret2:
-; WIN32: movb {{.*}}, (%eax)
+; WIN32: movb {{.*}}, ({{%e[abcd]x}})
; WIN32-NOT: popl %eax
; WIN32: {{retl$}}
@@ -56,8 +56,8 @@ entry:
define void @sret3(i8* sret %x, i8* %y) nounwind {
entry:
; WIN32-LABEL: _sret3:
-; WIN32: movb $42, (%eax)
-; WIN32-NOT: movb $13, (%eax)
+; WIN32: movb $42, ([[REG1:%e[abcd]x]])
+; WIN32-NOT: movb $13, ([[REG1]])
; WIN32-NOT: popl %eax
; WIN32: {{retl$}}
@@ -81,7 +81,7 @@ entry:
define void @sret4(%struct.S4* noalias sret %agg.result) {
entry:
; WIN32-LABEL: _sret4:
-; WIN32: movl $42, (%eax)
+; WIN32: movl $42, ({{%e[abcd]x}})
; WIN32-NOT: popl %eax
; WIN32: {{retl$}}
@@ -118,8 +118,8 @@ entry:
; The address of the return structure is passed as an implicit parameter.
; In the -O0 build, %eax is spilled at the beginning of the function, hence we
; should match both 4(%esp) and 8(%esp).
-; WIN32: {{[48]}}(%esp), %eax
-; WIN32: movl $42, (%eax)
+; WIN32: {{[48]}}(%esp), [[REG:%e[abcd]x]]
+; WIN32: movl $42, ([[REG]])
; WIN32: retl $4
}
@@ -230,8 +230,8 @@ define void @test8_f(i64 inreg %a, i64*
; WIN32-LABEL: _test8_f:
; WIN32: movl {{[0-9]+}}(%esp), %[[out:[a-z]+]]
-; WIN32-DAG: movl %edx, 4(%[[out]])
-; WIN32-DAG: movl %eax, (%[[out]])
+; WIN32-DAG: movl {{%e[abcd]x}}, 4(%[[out]])
+; WIN32-DAG: movl {{%e[abcd]x}}, (%[[out]])
; WIN32: calll _clobber_eax
; WIN32: movl {{.*}}, %eax
; WIN32: retl
Modified: llvm/trunk/test/CodeGen/XCore/dwarf_debug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/dwarf_debug.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/XCore/dwarf_debug.ll (original)
+++ llvm/trunk/test/CodeGen/XCore/dwarf_debug.ll Mon Oct 29 13:10:42 2018
@@ -4,11 +4,11 @@
; target triple = "xcore"
; CHECK-LABEL: f
-; CHECK: entsp 2
+; CHECK: entsp [[S:[0-9]+]]
; ...the prologue...
; CHECK: .loc 1 2 0 prologue_end # test.c:2:0
; CHECK: add r0, r0, 1
-; CHECK: retsp 2
+; CHECK: retsp [[S]]
define i32 @f(i32 %a) !dbg !4 {
entry:
%a.addr = alloca i32, align 4
Modified: llvm/trunk/test/DebugInfo/X86/parameters.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/parameters.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/parameters.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/parameters.ll Mon Oct 29 13:10:42 2018
@@ -1,7 +1,6 @@
; REQUIRES: object-emission
;
-; RUN: llc -mtriple=x86_64-unknown-linux-gnu -O0 -filetype=obj < %s > %t
-; RUN: llvm-dwarfdump -v -debug-info %t | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -O0 -filetype=obj %s -o - | llvm-dwarfdump -v -debug-info - | FileCheck %s
; Test case derived from compiling the following source with clang -g:
;
Modified: llvm/trunk/test/DebugInfo/X86/pieces-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/pieces-1.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/pieces-1.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/pieces-1.ll Mon Oct 29 13:10:42 2018
@@ -1,5 +1,4 @@
-; RUN: llc -O0 %s -filetype=obj -o %t.o
-; RUN: llvm-dwarfdump -debug-loc %t.o | FileCheck %s
+; RUN: llc -O0 %s -filetype=obj -o - | llvm-dwarfdump -debug-loc - | FileCheck %s
;
; rdar://problem/15928306
;
Modified: llvm/trunk/test/DebugInfo/X86/sdag-split-arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/sdag-split-arg.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/sdag-split-arg.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/sdag-split-arg.ll Mon Oct 29 13:10:42 2018
@@ -1,10 +1,10 @@
; RUN: llc -O0 -filetype=asm %s -o - | FileCheck %s
; Test large integral function arguments passed in multiple registers.
-; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 64 16] $ax
-; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 48 16] $r9w
-; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 32 16] $r10w
-; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 16 16] $r11w
-; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 0 16] $bx
+; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 64 16] ${{([a-d]x)|(si)|(di)|(bp)|(r[0-9]+w)}}
+; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 48 16] ${{([a-d]x)|(si)|(di)|(bp)|(r[0-9]+w)}}
+; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 32 16] ${{([a-d]x)|(si)|(di)|(bp)|(r[0-9]+w)}}
+; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 16 16] ${{([a-d]x)|(si)|(di)|(bp)|(r[0-9]+w)}}
+; CHECK: DEBUG_VALUE: foo:bar <- [DW_OP_LLVM_fragment 0 16] ${{([a-d]x)|(si)|(di)|(bp)|(r[0-9]+w)}}
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown"
Modified: llvm/trunk/test/DebugInfo/X86/vla.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/vla.ll?rev=345532&r1=345531&r2=345532&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/vla.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/vla.ll Mon Oct 29 13:10:42 2018
@@ -1,7 +1,7 @@
; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=asm %s -o - | FileCheck %s
; Ensure that we generate an indirect location for the variable length array a.
-; CHECK: ##DEBUG_VALUE: vla:a <- [DW_OP_deref] [$rcx+0]
-; CHECK: DW_OP_breg2
+; CHECK: ##DEBUG_VALUE: vla:a <- [DW_OP_deref] [{{\$r[a-z]+}}+0]
+; CHECK: DW_OP_breg{{[0-9]}}
; rdar://problem/13658587
;
; generated from:
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