[PATCH] D53190: ARM: avoid infinite combining loop

[Tim Northover via Phabricator via llvm-commits]

t.p.northover added a comment.

> It seems unlikely this is the only place where a problem with cycles during DAG combining/lowering pops up.

I think it's pretty rare. Mostly combines genuinely do simplify the DAG, or replace the lot with a target node. I did consider the latter but decided getting equivalent CodeGen out of it would be just as bad as (or worse than) the duplicated patterns for the subtraction.

> I guess an alternative would be to introduce a way to flag on ISD nodes "do not combine this node any further" as a more generic mechanism. I guess for that to work, some bit somewhere on the ISD node would be needed to store that info.

I hadn't considered an approach like that, but I think obeying such a flag would be pretty difficult. You don't just have to check the root of a combine, but every node involved. That probably means checks throughout the DAGCombiner.


Repository:
  rL LLVM

https://reviews.llvm.org/D53190