[PATCH] D52779: AMD BdVer2 (Piledriver) Initial Scheduler model

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Oct 27 08:08:15 PDT 2018


lebedev.ri updated this revision to Diff 171399.
lebedev.ri edited the summary of this revision.
lebedev.ri added a comment.

Rebased.
All further fixes/tuning after landing.

In https://reviews.llvm.org/D52779#1273934, @andreadb wrote:

> I am okay with accepting this patch


Thanks everyone!

> provided that you fix the store throughput.
>  If not in this patch, then it should definitely be addressed by a follow-up patch.
>  At the moment, your model assumes a maximum throughput of two store operations per cycle, which is incorrect.
>  You may want to do something similar to what we did for Jaguar, where the AGU scheduler is defined as a resource-group; we provide distinct definitions for the load/store AGEN pipes.
>  You can probaby do the same; if I understand correctly, that should be enough to fix your issue with the store throughput.

i *think* it may work, but indeed, that *should* be covered with tests, and there aren't any now, so i'm going to go with "fix afterwards."

> If for some reasons it takes time to fix, then you can commit this patch in the meantime.
>  Basically, you can commit this change for now, and raise a bug for the store throughput issue (so that we don't forget about fixing it).



> Thanks,
> Andrea



In https://reviews.llvm.org/D52779#1273946, @andreadb wrote:

> I forgot to write:
>  Please make sure to add all the bdver2 tests to llvm-mca - just copy the relevant ISA test files and update the RUN tags.


Yep, i understand :)

> Also, a test that shows the problematic store throughput would be nice.
>  Thanks!




Repository:
  rL LLVM

https://reviews.llvm.org/D52779

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86PfmCounters.td
  lib/Target/X86/X86ScheduleBdVer2.td
  test/CodeGen/X86/fma.ll
  test/CodeGen/X86/lwp-intrinsics.ll
  test/CodeGen/X86/lwp-schedule.ll
  test/CodeGen/X86/memset.ll
  test/CodeGen/X86/schedule-x86-64-shld.ll
  test/CodeGen/X86/tbm-schedule.ll
  test/CodeGen/X86/wide-fma-contraction.ll

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