[PATCH] D53784: [DAGCombiner] narrow vector binops when extraction is cheap

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, RKSimon, efriedma.
Herald added subscribers: kristof.beyls, javed.absar, mcrosier.

Narrowing vector binops came up in the demanded bits discussion in https://reviews.llvm.org/D52912.

I don't think we're going to be able to do this transform in IR as a canonicalization because of the risk of creating unsupported widths for vector ops, but we already have a DAG TLI hook to allow what I was hoping for: isExtractSubvectorCheap(). This is currently enabled for x86, ARM, and AArch64 (although only x86 has existing regression test diffs).

This is artificially limited to not look through bitcasts because there are so many test diffs already, but that's marked with a TODO and is a small follow-up.

We can add similar logic to narrow other ops. We need to adjust test/CodeGen/X86/avx2-schedule.ll to not be in this patch, but I figured it was worth posting now, so people can start looking at the other test diffs.


https://reviews.llvm.org/D53784

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/X86/2012-04-26-sdglue.ll
  test/CodeGen/X86/avx-logic.ll
  test/CodeGen/X86/avx-vzeroupper.ll
  test/CodeGen/X86/avx2-schedule.ll
  test/CodeGen/X86/avx512-hadd-hsub.ll
  test/CodeGen/X86/avx512-insert-extract.ll
  test/CodeGen/X86/avx512-skx-insert-subvec.ll
  test/CodeGen/X86/known-signbits-vector.ll
  test/CodeGen/X86/madd.ll
  test/CodeGen/X86/min-legal-vector-width.ll
  test/CodeGen/X86/sad.ll
  test/CodeGen/X86/shrink_vmul.ll
  test/CodeGen/X86/vec_int_to_fp.ll
  test/CodeGen/X86/vector-compare-all_of.ll
  test/CodeGen/X86/vector-compare-any_of.ll
  test/CodeGen/X86/vector-reduce-add.ll
  test/CodeGen/X86/vector-reduce-and.ll
  test/CodeGen/X86/vector-reduce-fadd-fast.ll
  test/CodeGen/X86/vector-reduce-fmul-fast.ll
  test/CodeGen/X86/vector-reduce-mul.ll
  test/CodeGen/X86/vector-reduce-or.ll
  test/CodeGen/X86/vector-reduce-xor.ll
  test/CodeGen/X86/vector-rotate-256.ll
  test/CodeGen/X86/vector-rotate-512.ll

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