[PATCH] D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor

[Tom Stellard via Phabricator via llvm-commits]

tstellar added inline comments.


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Comment at: test/CodeGen/AMDGPU/indirect-addressing-si.ll:390
+; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT2:[0-9]+]], s{{[0-9]+}}
+; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT1:[3]+]], s{{[0-9]+}}
+; GCN-DAG: v_mov_b32_e32 v[[VEC_ELT0:[0-9]+]], s[[S_ELT0]]
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jonpa wrote:
> tstellar wrote:
> > This [3] looks like a typo.
> :-)
> 
> I know that looks weird and suspected you might not like it. The problem was that the VEC_ELT1 register did not match properly further down. IIRC, there were different matches for different subtargets, so I had to force one of the matches into v3 (I suppose I should have removed the '+').
> 
> Please help me out and check if there is a better way, or if this is acceptable.
Ok, that's fine.  I would remove the + and also the brackets.


https://reviews.llvm.org/D49671