[PATCH] D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa updated this revision to Diff 171255.
jonpa added a reviewer: kparzysz.
jonpa added a comment.
Herald added subscribers: eraman, nhaehnle, jvesely.

I have gone through the tests as best as I can since the progress was slow. I will commit this in a few days if no one objects. Please take a look and review the test changes!

One test was beyond me: Hexagon/ps_call_nr.ll, which fails with  'LLVM ERROR: invalid instruction packet: slot error'.

First difference is after the packetizer, where it seems that a call has now been bundled for some reason, which I am guessing is wrong. Not sure at all how to fix.

   *** IR Dump After Hexagon Packetize   # *** IR Dump After Hexagon Packetize
   # Machine code for function f0: NoPHI   # Machine code for function f0: NoPHI
  
  bb.0.b0:                                bb.0.b0:
    successors: %bb.1(0x00000001); %bb.     successors: %bb.1(0x00000001); %bb.
  
    renamable $r0 = L2_loadri_io undef      renamable $r0 = L2_loadri_io undef
    BUNDLE implicit-def dead $p0, impli     BUNDLE implicit-def dead $p0, impli
    renamable $p0 = C2_bitsclri kille       renamable $p0 = C2_bitsclri kille
    PS_jmprettnew internal killed $p0       PS_jmprettnew internal killed $p0
    }                                       }
  
  bb.1.b2:                                bb.1.b2:
  ; predecessors: %bb.0                   ; predecessors: %bb.0
  
    BUNDLE implicit-def $r29, implicit-     BUNDLE implicit-def $r29, implicit-
    $r29 = S2_allocframe killed $r29(       $r29 = S2_allocframe killed $r29(
    $r3 = A2_tfrsi 0                        $r3 = A2_tfrsi 0
    $r4 = A2_tfrsi 0                        $r4 = A2_tfrsi 0
    }                                       }
    BUNDLE implicit-def $r1, implicit-d     BUNDLE implicit-def $r1, implicit-d
    renamable $r1 = L2_loadri_io kill       renamable $r1 = L2_loadri_io kill
    $r0 = A2_tfrsi @g0                      $r0 = A2_tfrsi @g0
    }                                       }
    BUNDLE implicit-def $r2, implicit-d |   BUNDLE implicit-def dead $r2, impli
    renamable $r2 = S2_extractu renam       renamable $r2 = S2_extractu renam
    renamable $r1 = S2_extractu renam       renamable $r1 = S2_extractu renam
                                        >     PS_call_nr @f1, <regmask $d8 $d9
    }                                       }
    PS_call_nr @f1, <regmask $d8 $d9 $d <
  
  # End machine code for function f0.     # End machine code for function f0.


https://reviews.llvm.org/D49671

Files:
  lib/CodeGen/ScheduleDAGInstrs.cpp
  test/CodeGen/AMDGPU/call-argument-types.ll
  test/CodeGen/AMDGPU/call-preserved-registers.ll
  test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
  test/CodeGen/AMDGPU/indirect-addressing-si.ll
  test/CodeGen/AMDGPU/inline-asm.ll
  test/CodeGen/AMDGPU/insert_vector_elt.ll
  test/CodeGen/AMDGPU/misched-killflags.mir
  test/CodeGen/AMDGPU/nested-calls.ll
  test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
  test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
  test/CodeGen/ARM/Windows/chkstk.ll
  test/CodeGen/ARM/Windows/memset.ll
  test/CodeGen/ARM/arm-and-tst-peephole.ll
  test/CodeGen/ARM/arm-shrink-wrapping.ll
  test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-ldm.ll
  test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
  test/CodeGen/ARM/cortex-a57-misched-vldm.ll
  test/CodeGen/ARM/fp16-instructions.ll
  test/CodeGen/ARM/select.ll
  test/CodeGen/ARM/twoaddrinstr.ll
  test/CodeGen/ARM/vcombine.ll
  test/CodeGen/ARM/vuzp.ll
  test/CodeGen/SystemZ/misched-readadvances.mir
  test/CodeGen/Thumb2/umulo-128-legalisation-lowering.ll
  test/CodeGen/Thumb2/umulo-64-legalisation-lowering.ll
  test/CodeGen/X86/lsr-loop-exit-cond.ll
  test/CodeGen/X86/phys-reg-local-regalloc.ll
  test/CodeGen/X86/schedule-x86-64-shld.ll
  test/CodeGen/X86/schedule-x86_32.ll

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