[llvm] r345299 - [WebAssembly] Use target-independent saturating add
Thomas Lively via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 25 12:06:14 PDT 2018
Author: tlively
Date: Thu Oct 25 12:06:13 2018
New Revision: 345299
URL: http://llvm.org/viewvc/llvm-project?rev=345299&view=rev
Log:
[WebAssembly] Use target-independent saturating add
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53721
Modified:
llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
Modified: llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td?rev=345299&r1=345298&r2=345299&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td (original)
+++ llvm/trunk/include/llvm/IR/IntrinsicsWebAssembly.td Thu Oct 25 12:06:13 2018
@@ -102,14 +102,6 @@ def int_wasm_atomic_notify:
// SIMD intrinsics
//===----------------------------------------------------------------------===//
-def int_wasm_add_saturate_signed :
- Intrinsic<[llvm_anyvector_ty],
- [LLVMMatchType<0>, LLVMMatchType<0>],
- [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_add_saturate_unsigned :
- Intrinsic<[llvm_anyvector_ty],
- [LLVMMatchType<0>, LLVMMatchType<0>],
- [IntrNoMem, IntrSpeculatable]>;
def int_wasm_sub_saturate_signed :
Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>],
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp?rev=345299&r1=345298&r2=345299&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Thu Oct 25 12:06:13 2018
@@ -115,6 +115,12 @@ WebAssemblyTargetLowering::WebAssemblyTa
setTruncStoreAction(T, MVT::f16, Expand);
}
+ // Support saturating add for i8x16 and i16x8
+ if (Subtarget->hasSIMD128())
+ for (auto T : {MVT::v16i8, MVT::v8i16})
+ for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
+ setOperationAction(Op, T, Legal);
+
for (auto T : {MVT::i32, MVT::i64}) {
// Expand unavailable integer operations.
for (auto Op :
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td?rev=345299&r1=345298&r2=345299&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td Thu Oct 25 12:06:13 2018
@@ -469,9 +469,9 @@ multiclass SIMDBinarySat<SDNode node, st
// Saturating integer addition: add_saturate_s / add_saturate_u
let isCommutable = 1 in {
defm ADD_SAT_S :
- SIMDBinarySat<int_wasm_add_saturate_signed, "add_saturate_s", 40>;
+ SIMDBinarySat<saddsat, "add_saturate_s", 40>;
defm ADD_SAT_U :
- SIMDBinarySat<int_wasm_add_saturate_unsigned, "add_saturate_u", 41>;
+ SIMDBinarySat<uaddsat, "add_saturate_u", 41>;
} // isCommutable = 1
// Saturating integer subtraction: sub_saturate_s / sub_saturate_u
Modified: llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll?rev=345299&r1=345298&r2=345299&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-intrinsics.ll Thu Oct 25 12:06:13 2018
@@ -16,11 +16,9 @@ target triple = "wasm32-unknown-unknown"
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.add.saturate.signed.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
- %a = call <16 x i8> @llvm.wasm.add.saturate.signed.v16i8(
- <16 x i8> %x, <16 x i8> %y
- )
+ %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %a
}
@@ -29,11 +27,9 @@ define <16 x i8> @add_sat_s_v16i8(<16 x
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.add.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
- %a = call <16 x i8> @llvm.wasm.add.saturate.unsigned.v16i8(
- <16 x i8> %x, <16 x i8> %y
- )
+ %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %a
}
@@ -106,11 +102,9 @@ define <16 x i8> @bitselect_v16i8(<16 x
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.add.saturate.signed.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
- %a = call <8 x i16> @llvm.wasm.add.saturate.signed.v8i16(
- <8 x i16> %x, <8 x i16> %y
- )
+ %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %a
}
@@ -119,11 +113,9 @@ define <8 x i16> @add_sat_s_v8i16(<8 x i
; SIMD128-NEXT: .result v128{{$}}
; SIMD128-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.add.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
- %a = call <8 x i16> @llvm.wasm.add.saturate.unsigned.v8i16(
- <8 x i16> %x, <8 x i16> %y
- )
+ %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %a
}
More information about the llvm-commits
mailing list