[PATCH] D53703: [LegalizeDAG] Remove dead SINT_TO_FP legalization code
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 25 10:46:54 PDT 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL345290: [LegalizeDAG] Remove dead SINT_TO_FP legalization code (authored by RKSimon, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D53703?vs=171091&id=171142#toc
Repository:
rL LLVM
https://reviews.llvm.org/D53703
Files:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Index: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2374,60 +2374,25 @@
LLVM_DEBUG(dbgs() << "Converting unsigned i64 to f32\n");
// For unsigned conversions, convert them to signed conversions using the
// algorithm from the x86_64 __floatundidf in compiler_rt.
- if (!isSigned) {
- SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
+ SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
- SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT);
- SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst);
- SDValue AndConst = DAG.getConstant(1, dl, SrcVT);
- SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Op0, AndConst);
- SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
-
- SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or);
- SDValue Slow = DAG.getNode(ISD::FADD, dl, DestVT, SignCvt, SignCvt);
-
- // TODO: This really should be implemented using a branch rather than a
- // select. We happen to get lucky and machinesink does the right
- // thing most of the time. This would be a good candidate for a
- // pseudo-op, or, even better, for whole-function isel.
- SDValue SignBitTest =
- DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
- DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
- return DAG.getSelect(dl, DestVT, SignBitTest, Slow, Fast);
- }
-
- // Otherwise, implement the fully general conversion.
-
- SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
- DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
- SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
- DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
- SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
- DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
- SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
- DAG.getConstant(UINT64_C(0), dl, MVT::i64),
- ISD::SETNE);
- SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
- SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
- DAG.getConstant(UINT64_C(0x0020000000000000), dl,
- MVT::i64),
- ISD::SETUGE);
- SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
- EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
-
- SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
- DAG.getConstant(32, dl, SHVT));
- SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
- SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
- SDValue TwoP32 =
- DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
- MVT::f64);
- SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
- SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
- SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
- SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
- return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
- DAG.getIntPtrConstant(0, dl));
+ SDValue ShiftConst = DAG.getConstant(1, dl, ShiftVT);
+ SDValue Shr = DAG.getNode(ISD::SRL, dl, SrcVT, Op0, ShiftConst);
+ SDValue AndConst = DAG.getConstant(1, dl, SrcVT);
+ SDValue And = DAG.getNode(ISD::AND, dl, SrcVT, Op0, AndConst);
+ SDValue Or = DAG.getNode(ISD::OR, dl, SrcVT, And, Shr);
+
+ SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Or);
+ SDValue Slow = DAG.getNode(ISD::FADD, dl, DestVT, SignCvt, SignCvt);
+
+ // TODO: This really should be implemented using a branch rather than a
+ // select. We happen to get lucky and machinesink does the right
+ // thing most of the time. This would be a good candidate for a
+ // pseudo-op, or, even better, for whole-function isel.
+ SDValue SignBitTest =
+ DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
+ DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
+ return DAG.getSelect(dl, DestVT, SignBitTest, Slow, Fast);
}
SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
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