[PATCH] D52833: [RISCV] Add codegen test for RV64 ALU operations

Lewis Revill via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Oct 25 08:14:24 PDT 2018

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lewis-revill abandoned this revision.
lewis-revill added a comment.

Closing this as it was obsolete a while ago once Alex's patches started.


Repository:
  rL LLVM

https://reviews.llvm.org/D52833

Previous message: [llvm] r345272 - [ARM] Use Cortex-A57 sched model for Cortex-A72
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