[PATCH] D44528: [PowerPC] Implement canCombineStoreAndExtract and provide the missing codegen patterns

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added inline comments.


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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:14307
+  // Only have combined stores for sub-word types on Power9.
+  if (BitWidth > 32 || (!Subtarget.hasP9Vector() && BitWidth != 32))
+    return false;
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I didn't take deep look at the implementation for this patch. The condition here seems not quite align with the comments. If the bitwidth is 32bit, we will combine the store and extract no matter if it is Power9 or not. I am not sure if this is by intention. 


Repository:
  rL LLVM

https://reviews.llvm.org/D44528