[PATCH] D53664: [GlobalISel] LegalizerHelper: Fix the incorrect alignment when splitting loads/stores in narrowScalar
Volkan Keles via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 24 12:08:01 PDT 2018
volkan created this revision.
volkan added reviewers: dsanders, bogner, jpaquette, aemerson, ab.
Herald added subscribers: javed.absar, kristof.beyls, rovka.
Herald added a reviewer: paquette.
https://reviews.llvm.org/D53664
Files:
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
test/CodeGen/AArch64/GlobalISel/legalize-load-store-s128-unaligned.mir
Index: test/CodeGen/AArch64/GlobalISel/legalize-load-store-s128-unaligned.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/GlobalISel/legalize-load-store-s128-unaligned.mir
@@ -0,0 +1,41 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - -run-pass=legalizer %s | FileCheck %s
+--- |
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64--"
+
+ define void @loadstore128_align4(i128* %src, i128* %dst) {
+ %val = load i128, i128* %src, align 4
+ store i128 %val, i128* %dst, align 4
+ ret void
+ }
+...
+---
+name: loadstore128_align4
+exposesReturnsTwice: false
+legalized: false
+tracksRegLiveness: true
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $x0, $x1
+
+ ; CHECK-LABEL: name: loadstore128_align4
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load 8 from %ir.src, align 4)
+ ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[C]](s64)
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[GEP]](p0) :: (load 8 from %ir.src + 8, align 4)
+ ; CHECK: G_STORE [[LOAD]](s64), [[COPY1]](p0) :: (store 8 into %ir.dst, align 4)
+ ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
+ ; CHECK: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY1]], [[C1]](s64)
+ ; CHECK: G_STORE [[LOAD1]](s64), [[GEP1]](p0) :: (store 8 into %ir.dst + 8, align 4)
+ ; CHECK: RET_ReallyLR
+ %0:_(p0) = COPY $x0
+ %1:_(p0) = COPY $x1
+ %2:_(s128) = G_LOAD %0(p0) :: (load 16 from %ir.src, align 4)
+ G_STORE %2(s128), %1(p0) :: (store 16 into %ir.dst, align 4)
+ RET_ReallyLR
+
+...
Index: lib/CodeGen/GlobalISel/LegalizerHelper.cpp
===================================================================
--- lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -467,12 +467,13 @@
unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
unsigned SrcReg = 0;
unsigned Adjustment = i * NarrowSize / 8;
+ unsigned Alignment = GreatestCommonDivisor64(
+ MMO.getAlignment(), MMO.getAlignment() + Adjustment);
MachineMemOperand *SplitMMO = MIRBuilder.getMF().getMachineMemOperand(
MMO.getPointerInfo().getWithOffset(Adjustment), MMO.getFlags(),
- NarrowSize / 8, i == 0 ? MMO.getAlignment() : NarrowSize / 8,
- MMO.getAAInfo(), MMO.getRanges(), MMO.getSyncScopeID(),
- MMO.getOrdering(), MMO.getFailureOrdering());
+ NarrowSize / 8, Alignment, MMO.getAAInfo(), MMO.getRanges(),
+ MMO.getSyncScopeID(), MMO.getOrdering(), MMO.getFailureOrdering());
MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
Adjustment);
@@ -509,12 +510,13 @@
for (int i = 0; i < NumParts; ++i) {
unsigned DstReg = 0;
unsigned Adjustment = i * NarrowSize / 8;
+ unsigned Alignment = GreatestCommonDivisor64(
+ MMO.getAlignment(), MMO.getAlignment() + Adjustment);
MachineMemOperand *SplitMMO = MIRBuilder.getMF().getMachineMemOperand(
MMO.getPointerInfo().getWithOffset(Adjustment), MMO.getFlags(),
- NarrowSize / 8, i == 0 ? MMO.getAlignment() : NarrowSize / 8,
- MMO.getAAInfo(), MMO.getRanges(), MMO.getSyncScopeID(),
- MMO.getOrdering(), MMO.getFailureOrdering());
+ NarrowSize / 8, Alignment, MMO.getAAInfo(), MMO.getRanges(),
+ MMO.getSyncScopeID(), MMO.getOrdering(), MMO.getFailureOrdering());
MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
Adjustment);
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