[llvm] r345130 - [llvm-exegesis] Implements a cache of Instruction objects.
Guillaume Chatelet via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 24 04:55:06 PDT 2018
Author: gchatelet
Date: Wed Oct 24 04:55:06 2018
New Revision: 345130
URL: http://llvm.org/viewvc/llvm-project?rev=345130&view=rev
Log:
[llvm-exegesis] Implements a cache of Instruction objects.
Modified:
llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp
llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp
llvm/trunk/tools/llvm-exegesis/lib/LlvmState.h
llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp
llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h
llvm/trunk/tools/llvm-exegesis/llvm-exegesis.cpp
llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
Modified: llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp?rev=345130&r1=345129&r2=345130&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp (original)
+++ llvm/trunk/tools/llvm-exegesis/lib/Latency.cpp Wed Oct 24 04:55:06 2018
@@ -49,7 +49,7 @@ computeAliasingInstructions(const LLVMSt
for (const unsigned OtherOpcode : Opcodes) {
if (OtherOpcode == Instr.Description->getOpcode())
continue;
- const Instruction OtherInstr(State, OtherOpcode);
+ const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode);
if (OtherInstr.hasMemoryOperands())
continue;
if (Instr.hasAliasingRegistersThrough(OtherInstr))
Modified: llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp?rev=345130&r1=345129&r2=345130&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp (original)
+++ llvm/trunk/tools/llvm-exegesis/lib/LlvmState.cpp Wed Oct 24 04:55:06 2018
@@ -38,6 +38,7 @@ LLVMState::LLVMState(const std::string &
}
RATC.reset(new RegisterAliasingTrackerCache(
getRegInfo(), getFunctionReservedRegs(getTargetMachine())));
+ IC.reset(new InstructionsCache(getInstrInfo(), getRATC()));
}
LLVMState::LLVMState()
Modified: llvm/trunk/tools/llvm-exegesis/lib/LlvmState.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/LlvmState.h?rev=345130&r1=345129&r2=345130&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/LlvmState.h (original)
+++ llvm/trunk/tools/llvm-exegesis/lib/LlvmState.h Wed Oct 24 04:55:06 2018
@@ -15,6 +15,7 @@
#ifndef LLVM_TOOLS_LLVM_EXEGESIS_LLVMSTATE_H
#define LLVM_TOOLS_LLVM_EXEGESIS_LLVMSTATE_H
+#include "MCInstrDescView.h"
#include "RegisterAliasing.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
@@ -57,11 +58,13 @@ public:
return *TargetMachine->getMCSubtargetInfo();
}
const RegisterAliasingTrackerCache &getRATC() const { return *RATC; }
+ const InstructionsCache &getIC() const { return *IC; }
private:
const ExegesisTarget *TheExegesisTarget;
std::unique_ptr<const llvm::TargetMachine> TargetMachine;
std::unique_ptr<const RegisterAliasingTrackerCache> RATC;
+ std::unique_ptr<const InstructionsCache> IC;
};
} // namespace exegesis
Modified: llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp?rev=345130&r1=345129&r2=345130&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp (original)
+++ llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.cpp Wed Oct 24 04:55:06 2018
@@ -95,10 +95,10 @@ const llvm::MCOperandInfo &Operand::getE
return *Info;
}
-Instruction::Instruction(const LLVMState &State, unsigned Opcode)
- : Description(&State.getInstrInfo().get(Opcode)),
- Name(State.getInstrInfo().getName(Opcode)) {
- const auto &RATC = State.getRATC();
+Instruction::Instruction(const llvm::MCInstrInfo &InstrInfo,
+ const RegisterAliasingTrackerCache &RATC,
+ unsigned Opcode)
+ : Description(&InstrInfo.get(Opcode)), Name(InstrInfo.getName(Opcode)) {
unsigned OpIndex = 0;
for (; OpIndex < Description->getNumOperands(); ++OpIndex) {
const auto &OpInfo = Description->opInfo_begin()[OpIndex];
@@ -262,6 +262,17 @@ void Instruction::dump(const llvm::MCReg
Stream << "- hasAliasingRegisters\n";
}
+InstructionsCache::InstructionsCache(const llvm::MCInstrInfo &InstrInfo,
+ const RegisterAliasingTrackerCache &RATC)
+ : InstrInfo(InstrInfo), RATC(RATC) {}
+
+const Instruction &InstructionsCache::getInstr(unsigned Opcode) const {
+ auto &Found = Instructions[Opcode];
+ if (!Found)
+ Found.reset(new Instruction(InstrInfo, RATC, Opcode));
+ return *Found;
+}
+
bool RegisterOperandAssignment::
operator==(const RegisterOperandAssignment &Other) const {
return std::tie(Op, Reg) == std::tie(Other.Op, Other.Reg);
Modified: llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h?rev=345130&r1=345129&r2=345130&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h (original)
+++ llvm/trunk/tools/llvm-exegesis/lib/MCInstrDescView.h Wed Oct 24 04:55:06 2018
@@ -20,8 +20,8 @@
#define LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
#include <random>
+#include <unordered_map>
-#include "LlvmState.h"
#include "RegisterAliasing.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/Optional.h"
@@ -94,7 +94,8 @@ struct Operand {
// A view over an MCInstrDesc offering a convenient interface to compute
// Register aliasing.
struct Instruction {
- Instruction(const LLVMState &State, unsigned Opcode);
+ Instruction(const llvm::MCInstrInfo &InstrInfo,
+ const RegisterAliasingTrackerCache &RATC, unsigned Opcode);
// Returns the Operand linked to this Variable.
// In case the Variable is tied, the primary (i.e. Def) Operand is returned.
@@ -145,6 +146,22 @@ struct Instruction {
llvm::BitVector AllUseRegs; // The set of all aliased use registers.
};
+// Instructions are expensive to instantiate. This class provides a cache of
+// Instructions with lazy construction.
+struct InstructionsCache {
+ InstructionsCache(const llvm::MCInstrInfo &InstrInfo,
+ const RegisterAliasingTrackerCache &RATC);
+
+ // Returns the Instruction object corresponding to this Opcode.
+ const Instruction &getInstr(unsigned Opcode) const;
+
+private:
+ const llvm::MCInstrInfo &InstrInfo;
+ const RegisterAliasingTrackerCache &RATC;
+ mutable std::unordered_map<unsigned, std::unique_ptr<Instruction>>
+ Instructions;
+};
+
// Represents the assignment of a Register to an Operand.
struct RegisterOperandAssignment {
RegisterOperandAssignment(const Operand *Operand, llvm::MCPhysReg Reg)
Modified: llvm/trunk/tools/llvm-exegesis/llvm-exegesis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-exegesis/llvm-exegesis.cpp?rev=345130&r1=345129&r2=345130&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-exegesis/llvm-exegesis.cpp (original)
+++ llvm/trunk/tools/llvm-exegesis/llvm-exegesis.cpp Wed Oct 24 04:55:06 2018
@@ -147,7 +147,7 @@ getOpcodesOrDie(const llvm::MCInstrInfo
// Generates code snippets for opcode `Opcode`.
static llvm::Expected<std::vector<BenchmarkCode>>
generateSnippets(const LLVMState &State, unsigned Opcode) {
- const Instruction Instr(State, Opcode);
+ const Instruction &Instr = State.getIC().getInstr(Opcode);
const llvm::MCInstrDesc &InstrDesc = *Instr.Description;
// Ignore instructions that we cannot run.
if (InstrDesc.isPseudo())
Modified: llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp?rev=345130&r1=345129&r2=345130&view=diff
==============================================================================
--- llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp (original)
+++ llvm/trunk/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp Wed Oct 24 04:55:06 2018
@@ -61,7 +61,7 @@ protected:
std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
randomGenerator().seed(0); // Initialize seed.
- const Instruction Instr(State, Opcode);
+ const Instruction &Instr = State.getIC().getInstr(Opcode);
auto CodeTemplateOrError = Generator.generateCodeTemplates(Instr);
EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
return std::move(CodeTemplateOrError.get());
@@ -341,7 +341,7 @@ TEST_F(UopsSnippetGeneratorTest, MemoryU
// - hasAliasingImplicitRegisters (execution is always serial)
// - hasAliasingRegisters
const unsigned Opcode = llvm::X86::MOVSB;
- const Instruction Instr(State, Opcode);
+ const Instruction &Instr = State.getIC().getInstr(Opcode);
auto Error = Generator.generateCodeTemplates(Instr).takeError();
EXPECT_TRUE((bool)Error);
llvm::consumeError(std::move(Error));
@@ -352,7 +352,7 @@ public:
FakeSnippetGenerator(const LLVMState &State) : SnippetGenerator(State) {}
Instruction createInstruction(unsigned Opcode) {
- return Instruction(State, Opcode);
+ return State.getIC().getInstr(Opcode);
}
private:
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