[PATCH] D53629: [GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes

[Amara Emerson via Phabricator via llvm-commits]

aemerson created this revision.
aemerson added reviewers: qcolombet, dsanders, ab, aditya_nandakumar, volkan, bogner, tstellar, aivchenk, jpaquette, rtereshin.
Herald added subscribers: kristof.beyls, javed.absar, rovka, nhaehnle, jvesely, arsenm.
Herald added a reviewer: paquette.

[GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes.

This patch restricts the capability of G_MERGE_VALUES, and uses the new G_BUILD_VECTOR and G_CONCAT_VECTOR opcodes instead in the appropriate places.

The MIRBuilder is modified to generate G_CONCAT when trying to create MERGE_VALUES of vectors.

This patch also includes AArch64 support for selecting G_BUILD_VECTOR of 4xs32 and 2xs64 vectors.


Repository:
  rL LLVM

https://reviews.llvm.org/D53629

Files:
  include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
  lib/CodeGen/GlobalISel/IRTranslator.cpp
  lib/CodeGen/GlobalISel/Legalizer.cpp
  lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  lib/CodeGen/MachineVerifier.cpp
  lib/Target/AArch64/AArch64InstructionSelector.cpp
  lib/Target/AArch64/AArch64LegalizerInfo.cpp
  lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  lib/Target/X86/X86InstructionSelector.cpp
  lib/Target/X86/X86LegalizerInfo.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  test/CodeGen/AArch64/GlobalISel/legalize-add.mir
  test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
  test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
  test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir
  test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
  test/CodeGen/AArch64/GlobalISel/select-build-vector.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values-build-vector.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
  test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
  test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
  test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll
  test/CodeGen/X86/GlobalISel/legalize-add-v256.mir
  test/CodeGen/X86/GlobalISel/legalize-add-v512.mir
  test/CodeGen/X86/GlobalISel/select-merge-vec256.mir
  test/CodeGen/X86/GlobalISel/select-merge-vec512.mir

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